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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [summary.log] - Rev 208

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User Configuration
-------------------------------------
Algorithm                               :       Minimum_Area
Memory Type                             :       True_Dual_Port_RAM
Port A Read Width               :       16
Port B Read Width               :       16
Port A Write Width              :       16
Port B Write Width              :       16
Memory Depth                    :       8192
--------------------------------------------------------------

Block RAM resource(s) (9K BRAMs)                : 0
Block RAM resource(s) (18K BRAMs)               : 8
--------------------------------------------------------------
Clock A Frequency               :  100
Port A Enable Rate              :  100
Port A Write Rate               :  50
----------------------------------------------------------
Estimated Power for IP : 7.975106 mW
----------------------------------------------------------

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [summary.log] - Rev 208