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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen_chipscope/] [chipscope_icon.v] - Rev 157
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/////////////////////////////////////////////////////////////////////////////// // Copyright (c) 2012 Xilinx, Inc. // All Rights Reserved /////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor : Xilinx // \ \ \/ Version : 14.2 // \ \ Application: Xilinx CORE Generator // / / Filename : chipscope_icon.v // /___/ /\ Timestamp : Tue Sep 25 21:59:11 CEST 2012 // \ \ / \ // \___\/\___\ // // Design Name: Verilog Synthesis Wrapper /////////////////////////////////////////////////////////////////////////////// // This wrapper is used to integrate with Project Navigator and PlanAhead `timescale 1ns/1ps module chipscope_icon( CONTROL0); inout [35 : 0] CONTROL0; endmodule