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https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen_chipscope/] [chipscope_ila.cdc] - Rev 158
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#ChipScope Core Generator Project File Version 3.0
#Tue Sep 25 22:02:47 CEST 2012
SignalExport.bus<0000>.channelList=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SignalExport.bus<0000>.name=TRIG0
SignalExport.bus<0000>.offset=0.0
SignalExport.bus<0000>.precision=0
SignalExport.bus<0000>.radix=Bin
SignalExport.bus<0000>.scaleFactor=1.0
SignalExport.clockChannel=CLK
SignalExport.dataEqualsTrigger=true
SignalExport.triggerChannel<0000><0000>=TRIG0[0]
SignalExport.triggerChannel<0000><0001>=TRIG0[1]
SignalExport.triggerChannel<0000><0002>=TRIG0[2]
SignalExport.triggerChannel<0000><0003>=TRIG0[3]
SignalExport.triggerChannel<0000><0004>=TRIG0[4]
SignalExport.triggerChannel<0000><0005>=TRIG0[5]
SignalExport.triggerChannel<0000><0006>=TRIG0[6]
SignalExport.triggerChannel<0000><0007>=TRIG0[7]
SignalExport.triggerChannel<0000><0008>=TRIG0[8]
SignalExport.triggerChannel<0000><0009>=TRIG0[9]
SignalExport.triggerChannel<0000><0010>=TRIG0[10]
SignalExport.triggerChannel<0000><0011>=TRIG0[11]
SignalExport.triggerChannel<0000><0012>=TRIG0[12]
SignalExport.triggerChannel<0000><0013>=TRIG0[13]
SignalExport.triggerChannel<0000><0014>=TRIG0[14]
SignalExport.triggerChannel<0000><0015>=TRIG0[15]
SignalExport.triggerChannel<0000><0016>=TRIG0[16]
SignalExport.triggerChannel<0000><0017>=TRIG0[17]
SignalExport.triggerChannel<0000><0018>=TRIG0[18]
SignalExport.triggerChannel<0000><0019>=TRIG0[19]
SignalExport.triggerChannel<0000><0020>=TRIG0[20]
SignalExport.triggerChannel<0000><0021>=TRIG0[21]
SignalExport.triggerChannel<0000><0022>=TRIG0[22]
SignalExport.triggerChannel<0000><0023>=TRIG0[23]
SignalExport.triggerPort<0000>.name=TRIG0
SignalExport.triggerPortCount=1
SignalExport.triggerPortIsData<0000>=true
SignalExport.triggerPortWidth<0000>=24
SignalExport.type=ila
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