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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen_chipscope/] [chipscope_ila.ucf] - Rev 157
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## Clock constraints#NET "CLK" TNM_NET = D_CLK ;INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;TIMESPEC TS_D2_TO_T2 = FROM D2_CLK TO "FFS" TIG;TIMESPEC TS_J2_TO_D2 = FROM "FFS" TO D2_CLK TIG;TIMESPEC TS_J3_TO_D2 = FROM "FFS" TO D2_CLK TIG;TIMESPEC TS_J4_TO_D2 = FROM "FFS" TO D2_CLK TIG;## Input keep/save net constraints#NET "TRIG0<*" S;NET "TRIG0<*" KEEP;