URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen_chipscope/] [coregen.log] - Rev 157
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Welcome to Xilinx CORE Generator.Help system initialized.The IP Catalog has been reloaded.Wrote CGP file for project 'coregen'.Customize and GenerateINFO:sim:172 - Generating IP...WARNING:sim:100 - The Simulation File Type <Behavioral> is not valid for thiscore. Overriding with File Type <structural>.Applying current project options...Finished applying current project options.Customizing IP...Release 14.2 - Xilinx CORE Generator IP GUI Launcher P.28xd (lin64)Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.terminate called after throwing an instance of 'Port_ThrException::Exception'Finished Customizing.Generating IP...WARNING:sim:100 - The Simulation File Type <Behavioral> is not valid for thiscore. Overriding with File Type <structural>.Configuring files for chipscope_icon root...Gathering HDL files for chipscope_icon root...Creating XST project for chipscope_icon...Creating XST script file for chipscope_icon...Creating XST instantiation file for chipscope_icon...Running XST for chipscope_icon...XST: HDL ParsingXST: HDL ElaborationXST: HDL SynthesisXST: Advanced HDL SynthesisXST: Low Level SynthesisXST: Design SummaryNot generating VHDL wrapperGenerating Verilog wrapperSkipping VHDL instantiation template for chipscope_icon...Creating ISE instantiation template for chipscope_icon...Finished Generation.Generating IP instantiation template...Generating ASY schematic symbol...INFO:sim:949 - Finished generation of ASY schematic symbol.Generating metadata file...Generating ISE project...XCO file found: chipscope_icon.xcoXMDF file found: chipscope_icon_xmdf.tclAdding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/chipscope_icon.asy -view all -origin_typeimportedAdding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/chipscope_icon.ngc -view all -origin_type createdChecking file"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/chipscope_icon.ngc" for project device match ...File"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/chipscope_icon.ngc" device information matchesproject device.Adding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/chipscope_icon.v -view all -origin_type createdINFO:HDLCompiler:1845 - Analyzing Verilog file"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/chipscope_icon.v" into library workINFO:ProjectMgmt - Parsing design hierarchy completed successfully.Adding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/chipscope_icon.veo -view all -origin_typeimportedINFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.Please set the new top explicitly by running the "project set top" command.To re-calculate the new top automatically, set the "Auto Implementation Top"property to true.Top level has been set to "/chipscope_icon"Generating README file...Generating FLIST file...INFO:sim:948 - Finished FLIST file generation.Launching README viewer...Moving files to output directory...Finished moving files to output directorySaved CGP file for project 'coregen'.Customize and GenerateINFO:sim:172 - Generating IP...WARNING:sim:100 - The Simulation File Type <Behavioral> is not valid for thiscore. Overriding with File Type <structural>.Applying current project options...Finished applying current project options.Customizing IP...Release 14.2 - Xilinx CORE Generator IP GUI Launcher P.28xd (lin64)Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.terminate called after throwing an instance of 'Port_ThrException::Exception'Finished Customizing.Generating IP...WARNING:sim:100 - The Simulation File Type <Behavioral> is not valid for thiscore. Overriding with File Type <structural>.Configuring files for chipscope_ila root...Gathering HDL files for chipscope_ila root...Creating XST project for chipscope_ila...Creating XST script file for chipscope_ila...Creating XST instantiation file for chipscope_ila...Running XST for chipscope_ila...XST: HDL ParsingXST: HDL ElaborationXST: HDL SynthesisXST: Advanced HDL SynthesisXST: Low Level SynthesisXST: Design SummaryNot generating VHDL wrapperGenerating Verilog wrapperSkipping VHDL instantiation template for chipscope_ila...Creating ISE instantiation template for chipscope_ila...Finished Generation.Generating IP instantiation template...Generating ASY schematic symbol...INFO:sim:949 - Finished generation of ASY schematic symbol.Generating metadata file...Generating ISE project...XCO file found: chipscope_ila.xcoXMDF file found: chipscope_ila_xmdf.tclAdding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/chipscope_ila.asy -view all -origin_type importedAdding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/chipscope_ila.ngc -view all -origin_type createdChecking file"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/chipscope_ila.ngc" for project device match ...File"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/chipscope_ila.ngc" device information matchesproject device.Adding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/chipscope_ila.v -view all -origin_type createdINFO:HDLCompiler:1845 - Analyzing Verilog file"/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/chipscope_ila.v" into library workINFO:ProjectMgmt - Parsing design hierarchy completed successfully.Adding/home/pitchu/Projects/verilog/openMSP430/fpga/zxilinx_avnet_lx9microbard/rtl/verilog/coregen_chipscope/tmp/_cg/chipscope_ila.veo -view all -origin_type importedINFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.Please set the new top explicitly by running the "project set top" command.To re-calculate the new top automatically, set the "Auto Implementation Top"property to true.Top level has been set to "/chipscope_ila"Generating README file...Generating FLIST file...INFO:sim:948 - Finished FLIST file generation.Launching README viewer...Moving files to output directory...Finished moving files to output directorySaved CGP file for project 'coregen'.Saved CGP file for project 'coregen'.Closed project file.