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# ----------------------------------------------------------------------------
#     _____
#    /     \
#   /____   \____
#  / \===\   \==/
# /___\===\___\/  AVNET Design Resource Center
#      \======/         www.em.avnet.com/s6microboard
#       \====/    
# ----------------------------------------------------------------------------
# 
#  Created With Avnet UCF Generator V0.3.0 
#     Date: Friday, November 12, 2010 
#     Time: 4:11:53 PM 
#
#  Updates
#     4 Jan 2011 -- added DIPs; changed IOSTANDARD for LEDs and LPDDR
#        11 Jan 2011 -- Changed IOSTANDARD for DIPs to LVCMOS33.
#                                   Replaced '#' on the end of net names with '_n'
#    14 Jan 2011 -- Added I2C for CDCE913 clock chip
#                   Added formatting and section breaks
#    27 Jan 2011 -- Updated URL for PMODs
#    04 Aug 2011 -- Renaming USER_RESET_N to USER_RESET since it is not low-enabled;
#                   Added extra comment on Ethernet PHY RXD pull-ups
#                   Removed extraneous quote mark in I2C port syntax
# 
#  This design is the property of Avnet.  Publication of this
#  design is not authorized without written consent from Avnet.
#  
#  Please direct any questions to:
#     Avnet Technical Forums
#     http://community.em.avnet.com/t5/Spartan-6-LX9-MicroBoard/bd-p/Spartan-6LX9MicroBoard
#
#     Avnet Centralized Technical Support
#     Centralized-Support@avnet.com
#     1-800-422-9023
# 
#  Disclaimer:
#     Avnet, Inc. makes no warranty for the use of this code or design.
#     This code is provided  "As Is". Avnet, Inc assumes no responsibility for
#     any errors, which may appear in this code, nor does it make a commitment
#     to update the information contained herein. Avnet, Inc specifically
#     disclaims any implied warranties of fitness for a particular purpose.
#                      Copyright(c) 2011 Avnet, Inc.
#                              All rights reserved.
# 
# ----------------------------------------------------------------------------

############################################################################
# PROGRAM MEMORY PLACEMENT
############################################################################

# ROM Block Assignments
INST "ram_16x2k_pmem/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram"  LOC = "RAMB16_X0Y20";
INST "ram_16x2k_pmem/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram"  LOC = "RAMB16_X0Y22";
#INST "ram_16x2k_pmem/B8"  LOC = "RAMB16_X0Y22"; 


############################################################################
# VCC AUX VOLTAGE 
############################################################################
CONFIG VCCAUX=3.3;

############################################################################    
# User Reset Push Button
#   Ignore the timing for this signal
#   Internal pull-down required since external resistor is not populated
############################################################################    
NET USER_RESET      LOC = V4  | IOSTANDARD = LVCMOS33 | PULLDOWN;    # "USER_RESET"
NET USER_RESET      TIG;

############################################################################    
# Micron N25Q128 SPI Flash
#   This is a Multi-I/O Flash.  Several pins have dual purposes
#   depending on the mode.
############################################################################    
NET SPI_SCK           LOC = R15 | IOSTANDARD = LVCMOS33;               # "CCLK"
NET SPI_CS_n          LOC = V3  | IOSTANDARD = LVCMOS33;               # "SPI_CS#"
NET SPI_MOSI_MISO0    LOC = T13 | IOSTANDARD = LVCMOS33;               # "MOSI_MISO0"
NET SPI_MISO_MISO1    LOC = R13 | IOSTANDARD = LVCMOS33;               # "D0_DIN_MISO_MISO1"
NET SPI_Wn_MISO2      LOC = T14 | IOSTANDARD = LVCMOS33;               # "D1_MISO2"
NET SPI_HOLDn_MISO3   LOC = V14 | IOSTANDARD = LVCMOS33;               # "D2_MISO3"

############################################################################    
# Texas Instruments CDCE913 Triple-Output PLL Clock Chip
#   Y1: 40 MHz, USER_CLOCK can be used as external configuration clock
#   Y2: 66.667 MHz
#   Y3: 100 MHz 
############################################################################    
NET USER_CLOCK        LOC = V10 | IOSTANDARD = LVCMOS33;               # "USER_CLOCK"
NET CLOCK_Y2          LOC = K15 | IOSTANDARD = LVCMOS33;               # "CLOCK_Y2"
NET CLOCK_Y3          LOC = C10 | IOSTANDARD = LVCMOS33;               # "CLOCK_Y3"

NET USER_CLOCK TNM_NET = USER_CLOCK;
TIMESPEC TS_USER_CLOCK = PERIOD USER_CLOCK 40000 kHz;
#NET CLOCK_Y2 TNM_NET = CLOCK_Y2;
#TIMESPEC TS_CLOCK_Y2 = PERIOD CLOCK_Y2 66666.7 kHz;
#NET CLOCK_Y3 TNM_NET = CLOCK_Y3;
#TIMESPEC TS_CLOCK_Y3 = PERIOD CLOCK_Y3 100000 kHz;

############################################################################    
# The following oscillator is not populated in production but the footprint
# is compatible with the Maxim DS1088LU                 
############################################################################    
NET BACKUP_CLK        LOC = R8  | IOSTANDARD = LVCMOS33;               # "MAIN_CLK"

############################################################################    
# User DIP Switch x4
#   Internal pull-down required since external resistor is not populated
############################################################################    
NET GPIO_DIP1         LOC = B3  | IOSTANDARD = LVCMOS33 | PULLDOWN;    # "GPIO_DIP1"
NET GPIO_DIP2         LOC = A3  | IOSTANDARD = LVCMOS33 | PULLDOWN;    # "GPIO_DIP2"
NET GPIO_DIP3         LOC = B4  | IOSTANDARD = LVCMOS33 | PULLDOWN;    # "GPIO_DIP3"
NET GPIO_DIP4         LOC = A4  | IOSTANDARD = LVCMOS33 | PULLDOWN;    # "GPIO_DIP4"

############################################################################    
# User LEDs                     
############################################################################    
NET GPIO_LED1         LOC = P4  | IOSTANDARD = LVCMOS18;               # "GPIO_LED1"
NET GPIO_LED2         LOC = L6  | IOSTANDARD = LVCMOS18;               # "GPIO_LED2"
NET GPIO_LED3         LOC = F5  | IOSTANDARD = LVCMOS18;               # "GPIO_LED3"
NET GPIO_LED4         LOC = C2  | IOSTANDARD = LVCMOS18;               # "GPIO_LED4"

############################################################################    
# Silicon Labs CP2102 USB-to-UART Bridge Chip
############################################################################    
NET USB_RS232_RXD     LOC = R7  | IOSTANDARD = LVCMOS33;               # "USB_RS232_RXD"
NET USB_RS232_TXD     LOC = T7  | IOSTANDARD = LVCMOS33;               # "USB_RS232_TXD"

############################################################################    
# Texas Instruments CDCE913 programming port
#   Internal pull-ups required since external resistors are not populated
############################################################################    
NET SCL               LOC=P12   | IOSTANDARD = LVCMOS33 | PULLUP;    # "SCL"
NET SDA               LOC=U13   | IOSTANDARD = LVCMOS33 | PULLUP;    # "SDA"

############################################################################    
# Micron MT46H32M16LFBF-5 LPDDR                 
############################################################################    
CONFIG MCB_PERFORMANCE= STANDARD;
# Addresses
NET LPDDR_A0          LOC = J7  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_A0"
NET LPDDR_A1          LOC = J6  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_A1"
NET LPDDR_A2          LOC = H5  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_A2"
NET LPDDR_A3          LOC = L7  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_A3"
NET LPDDR_A4          LOC = F3  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_A4"
NET LPDDR_A5          LOC = H4  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_A5"
NET LPDDR_A6          LOC = H3  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_A6"
NET LPDDR_A7          LOC = H6  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_A7"
NET LPDDR_A8          LOC = D2  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_A8"
NET LPDDR_A9          LOC = D1  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_A9"
NET LPDDR_A10         LOC = F4  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_A10"
NET LPDDR_A11         LOC = D3  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_A11"
NET LPDDR_A12         LOC = G6  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_A12"
NET LPDDR_BA0         LOC = F2  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_BA0"
NET LPDDR_BA1         LOC = F1  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_BA1"
# Data                                                                  
NET LPDDR_DQ0         LOC = L2  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_DQ0"
NET LPDDR_DQ1         LOC = L1  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_DQ1"
NET LPDDR_DQ2         LOC = K2  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_DQ2"
NET LPDDR_DQ3         LOC = K1  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_DQ3"
NET LPDDR_DQ4         LOC = H2  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_DQ4"
NET LPDDR_DQ5         LOC = H1  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_DQ5"
NET LPDDR_DQ6         LOC = J3  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_DQ6"
NET LPDDR_DQ7         LOC = J1  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_DQ7"
NET LPDDR_DQ8         LOC = M3  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_DQ8"
NET LPDDR_DQ9         LOC = M1  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_DQ9"
NET LPDDR_DQ10        LOC = N2  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_DQ10"
NET LPDDR_DQ11        LOC = N1  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_DQ11"
NET LPDDR_DQ12        LOC = T2  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_DQ12"
NET LPDDR_DQ13        LOC = T1  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_DQ13"
NET LPDDR_DQ14        LOC = U2  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_DQ14"
NET LPDDR_DQ15        LOC = U1  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_DQ15"
NET LPDDR_LDM         LOC = K3  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_LDM"
NET LPDDR_UDM         LOC = K4  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_UDM"
NET LPDDR_LDQS        LOC = L4  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_LDQS"
NET LPDDR_UDQS        LOC = P2  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_UDQS"
# Clock
NET LPDDR_CK_N        LOC = G1  | IOSTANDARD = DIFF_MOBILE_DDR;        # "LPDDR_CK_N"
NET LPDDR_CK_P        LOC = G3  | IOSTANDARD = DIFF_MOBILE_DDR;        # "LPDDR_CK_P"
NET LPDDR_CKE         LOC = H7  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_CKE"
# Control
NET LPDDR_CAS_n       LOC = K5  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_CAS#"
NET LPDDR_RAS_n       LOC = L5  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_RAS#"
NET LPDDR_WE_n        LOC = E3  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_WE#"
NET LPDDR_RZQ         LOC = N4  | IOSTANDARD = MOBILE_DDR;             # "LPDDR_RZQ"
############################################################################    
# All the IO resources in an IO tile which contains DQSP/UDQSP are used         
# irrespective of a single-ended or differential DQS design. Any signal that    
# is connected to the free pin of the same IO tile in a single-ended design     
# will be unrouted. Hence, the IOB cannot used as general pupose IO.                    
############################################################################    
CONFIG PROHIBIT = P1,L3;

############################################################################    
# National Semiconductor DP83848J 10/100 Ethernet PHY                   
#   Pull-ups on RXD are necessary to set the PHY AD to 11110b.
#   Must keep the PHY from defaulting to PHY AD = 00000b      
#   because this is Isolate Mode                              
############################################################################    
NET ETH_COL           LOC = M18 | IOSTANDARD = LVCMOS33 | PULLDOWN;    # "ETH_COL"
NET ETH_CRS           LOC = N17 | IOSTANDARD = LVCMOS33 | PULLDOWN;    # "ETH_CRS"
NET ETH_MDC           LOC = M16 | IOSTANDARD = LVCMOS33;               # "ETH_MDC"
NET ETH_MDIO          LOC = L18 | IOSTANDARD = LVCMOS33;               # "ETH_MDIO"
NET ETH_RESET_n       LOC = T18 | IOSTANDARD = LVCMOS33 | TIG;         # "ETH_RESET#"
NET ETH_RX_CLK        LOC = L15 | IOSTANDARD = LVCMOS33;               # "ETH_RX_CLK"
NET ETH_RX_D0         LOC = T17 | IOSTANDARD = LVCMOS33 | PULLUP;      # "ETH_RX_D0"
NET ETH_RX_D1         LOC = N16 | IOSTANDARD = LVCMOS33 | PULLUP;      # "ETH_RX_D1"
NET ETH_RX_D2         LOC = N15 | IOSTANDARD = LVCMOS33 | PULLUP;      # "ETH_RX_D2"
NET ETH_RX_D3         LOC = P18 | IOSTANDARD = LVCMOS33 | PULLUP;      # "ETH_RX_D3"
NET ETH_RX_DV         LOC = P17 | IOSTANDARD = LVCMOS33;               # "ETH_RX_DV"
NET ETH_RX_ER         LOC = N18 | IOSTANDARD = LVCMOS33;               # "ETH_RX_ER"
NET ETH_TX_CLK        LOC = H17 | IOSTANDARD = LVCMOS33;               # "ETH_TX_CLK"
NET ETH_TX_D0         LOC = K18 | IOSTANDARD = LVCMOS33;               # "ETH_TX_D0"
NET ETH_TX_D1         LOC = K17 | IOSTANDARD = LVCMOS33;               # "ETH_TX_D1"
NET ETH_TX_D2         LOC = J18 | IOSTANDARD = LVCMOS33;               # "ETH_TX_D2"
NET ETH_TX_D3         LOC = J16 | IOSTANDARD = LVCMOS33;               # "ETH_TX_D3"
NET ETH_TX_EN         LOC = L17 | IOSTANDARD = LVCMOS33;               # "ETH_TX_EN"

############################################################################    
# Peripheral Modules and GPIO
#   Peripheral Modules (PMODs) were invented by Digilent Inc. as small, 
#   inexpensive add-on boards for FPGA development boards. With costs 
#   starting as low as $10, PMODs allow you to add a number of capabilities 
#   to your board, including A/D, D/A, Wireless Radio, SD Card, 2x16 
#   Character LCD and a variety of LEDs, switches, and headers. See the 
#   complete library of Digilent PMODs at 
#     https://www.digilentinc.com/PMODs
############################################################################    
# Connector J5
NET PMOD1_P1          LOC = F15 | IOSTANDARD = LVCMOS33;               # "PMOD1_P1"
NET PMOD1_P2          LOC = F16 | IOSTANDARD = LVCMOS33;               # "PMOD1_P2"
NET PMOD1_P3          LOC = C17 | IOSTANDARD = I2C | PULLUP;           # "PMOD1_P3"
NET PMOD1_P4          LOC = C18 | IOSTANDARD = I2C | PULLUP;           # "PMOD1_P4"
NET PMOD1_P7          LOC = F14 | IOSTANDARD = LVCMOS33;               # "PMOD1_P7"
NET PMOD1_P8          LOC = G14 | IOSTANDARD = LVCMOS33;               # "PMOD1_P8"
NET PMOD1_P9          LOC = D17 | IOSTANDARD = LVCMOS33;               # "PMOD1_P9"
NET PMOD1_P10         LOC = D18 | IOSTANDARD = LVCMOS33;               # "PMOD1_P10"

# Connector J4
NET PMOD2_P1          LOC = H12 | IOSTANDARD = LVCMOS33;               # "PMOD2_P1"
NET PMOD2_P2          LOC = G13 | IOSTANDARD = LVCMOS33;               # "PMOD2_P2"
NET PMOD2_P3          LOC = E16 | IOSTANDARD = LVCMOS33;               # "PMOD2_P3"
NET PMOD2_P4          LOC = E18 | IOSTANDARD = LVCMOS33;               # "PMOD2_P4"
NET PMOD2_P7          LOC = K12 | IOSTANDARD = LVCMOS33;               # "PMOD2_P7"
NET PMOD2_P8          LOC = K13 | IOSTANDARD = LVCMOS33;               # "PMOD2_P8"
NET PMOD2_P9          LOC = F17 | IOSTANDARD = LVCMOS33;               # "PMOD2_P9"
NET PMOD2_P10         LOC = F18 | IOSTANDARD = LVCMOS33;               # "PMOD2_P10"