OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [coregen/] [ram_8x512_lo.sym] - Rev 126

Go to most recent revision | Compare with Previous | Blame | View Log

VERSION 5
BEGIN SYMBOL ram_8x512_lo
SYMBOLTYPE BLOCK
TIMESTAMP 2009 4 6 14 53 7
SYMPIN 0 48 Input addr[8:0]
SYMPIN 0 80 Input din[7:0]
SYMPIN 0 112 Input we
SYMPIN 0 144 Input en
SYMPIN 0 240 Input clk
SYMPIN 352 48 Output dout[7:0]
RECTANGLE N 32 0 320 272 
BEGIN DISPLAY 36 48 PIN addr[8:0] ATTR PinName
    FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 0 48 32 48 
END LINE
BEGIN DISPLAY 36 80 PIN din[7:0] ATTR PinName
    FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 0 80 32 80 
END LINE
BEGIN DISPLAY 36 112 PIN we ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 0 112 32 112 
BEGIN DISPLAY 36 144 PIN en ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 0 144 32 144 
BEGIN DISPLAY 36 240 PIN clk ATTR PinName
    FONT 24 "Arial"
END DISPLAY
LINE N 0 240 32 240 
BEGIN DISPLAY 316 48 PIN dout[7:0] ATTR PinName
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 320 48 352 48 
END LINE
END SYMBOL

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.