Subversion Repositories openmsp430

The following files were generated for 'ram_8x512_lo' in directory 
/home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coregen/:

ram_8x512_lo.asy:
   Graphical symbol information file. Used by the ISE tools and some
   third party tools to create a symbol representing the core.

ram_8x512_lo.ngc:
   Binary Xilinx implementation netlist file containing the information
   required to implement the module in a Xilinx (R) FPGA.

ram_8x512_lo.sym:
   Please see the core data sheet.

ram_8x512_lo.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

ram_8x512_lo.veo:
   VEO template file containing code that can be used as a model for
   instantiating a CORE Generator module in a Verilog design.

ram_8x512_lo.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

ram_8x512_lo_flist.txt:
   Text file listing all of the output files produced when a customized
   core was generated in the CORE Generator.

ram_8x512_lo_readme.txt:
   Text file indicating the files generated and how they are used.

ram_8x512_lo_xmdf.tcl:
   ISE Project Navigator interface file. ISE uses this file to determine
   how the files output by CORE Generator for the core can be integrated
   into your ISE project.


Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.