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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [coregen/] [rom_8x2k_hi.sym] - Rev 204
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VERSION 5
BEGIN SYMBOL rom_8x2k_hi
SYMBOLTYPE BLOCK
TIMESTAMP 2009 5 27 15 20 33
SYMPIN 0 48 Input addr[10:0]
SYMPIN 0 80 Input din[7:0]
SYMPIN 0 112 Input we
SYMPIN 0 144 Input en
SYMPIN 0 240 Input clk
SYMPIN 352 48 Output dout[7:0]
RECTANGLE N 32 0 320 272
BEGIN DISPLAY 36 48 PIN addr[10:0] ATTR PinName
FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 0 48 32 48
END LINE
BEGIN DISPLAY 36 80 PIN din[7:0] ATTR PinName
FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 0 80 32 80
END LINE
BEGIN DISPLAY 36 112 PIN we ATTR PinName
FONT 24 "Arial"
END DISPLAY
LINE N 0 112 32 112
BEGIN DISPLAY 36 144 PIN en ATTR PinName
FONT 24 "Arial"
END DISPLAY
LINE N 0 144 32 144
BEGIN DISPLAY 36 240 PIN clk ATTR PinName
FONT 24 "Arial"
END DISPLAY
LINE N 0 240 32 240
BEGIN DISPLAY 316 48 PIN dout[7:0] ATTR PinName
ALIGNMENT RIGHT
FONT 24 "Arial"
END DISPLAY
BEGIN LINE W 320 48 352 48
END LINE
END SYMBOL
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