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#=============================================================================
# Copyright (C) 2001 Authors
#
# This source file may be used and distributed without restriction provided
# that this copyright statement is not removed from the file and that any
# derivative work contains the original copyright notice and the associated
# disclaimer.
#
# This source file is free software; you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published
# by the Free Software Foundation; either version 2.1 of the License, or
# (at your option) any later version.
#
# This source is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
# License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with this source; if not, write to the Free Software Foundation,
# Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
#
#-----------------------------------------------------------------------------
# 
# File Name: openMSP430_fpga.ucf
# 
# Author(s):
#             - Olivier Girard,    olgirard@gmail.com
#
#-----------------------------------------------------------------------------
# $Rev: 153 $
# $LastChangedBy: olivier.girard $
# $LastChangedDate: 2012-08-22 00:27:18 +0200 (Wed, 22 Aug 2012) $
#=============================================================================

#-----------------------------------------------------------------------------#
# Clock configuration & ROM Block Assignments                                 #
#-----------------------------------------------------------------------------#

# CLOCKS Definition
NET "CLK_50MHz" PERIOD = 20 nS LOW 10.0 nS;
#NET "dcm_clk"  PERIOD = 50 nS LOW 25.0 nS;
#NET "clk_sys"  PERIOD = 50 nS LOW 25.0 nS;
NET "dcm_clk"  PERIOD = 40 nS LOW 20.0 nS;
NET "clk_sys"  PERIOD = 40 nS LOW 20.0 nS;


# DCM Configuration
#INST dcm_adv_clk_main CLKFX_DIVIDE          = 5;
#INST dcm_adv_clk_main CLKFX_MULTIPLY        = 2;
#INST dcm_adv_clk_main CLK_FEEDBACK          = NONE;
#INST dcm_adv_clk_main CLKDV_DIVIDE          = 2.5;
#INST dcm_adv_clk_main CLKIN_DIVIDE_BY_2     = FALSE;
#INST dcm_adv_clk_main CLKIN_PERIOD          = 20.000000;
#INST dcm_adv_clk_main CLKOUT_PHASE_SHIFT    = NONE;
#INST dcm_adv_clk_main DESKEW_ADJUST         = SYSTEM_SYNCHRONOUS;
#INST dcm_adv_clk_main DFS_FREQUENCY_MODE    = LOW;
#INST dcm_adv_clk_main DLL_FREQUENCY_MODE    = LOW;
#INST dcm_adv_clk_main DUTY_CYCLE_CORRECTION = TRUE;
#INST dcm_adv_clk_main FACTORY_JF            = C080;
#INST dcm_adv_clk_main PHASE_SHIFT           = 0;
#INST dcm_adv_clk_main STARTUP_WAIT          = FALSE;
INST dcm_adv_clk_main CLK_FEEDBACK = 1X;
INST dcm_adv_clk_main CLKDV_DIVIDE = 2.5;
INST dcm_adv_clk_main CLKFX_DIVIDE = 1;
INST dcm_adv_clk_main CLKFX_MULTIPLY = 4;
INST dcm_adv_clk_main CLKIN_DIVIDE_BY_2 = FALSE;
INST dcm_adv_clk_main CLKIN_PERIOD = 20.000;
INST dcm_adv_clk_main CLKOUT_PHASE_SHIFT = NONE;
INST dcm_adv_clk_main DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
INST dcm_adv_clk_main DFS_FREQUENCY_MODE = LOW;
INST dcm_adv_clk_main DLL_FREQUENCY_MODE = LOW;
INST dcm_adv_clk_main DUTY_CYCLE_CORRECTION = TRUE;
INST dcm_adv_clk_main FACTORY_JF = 8080;
INST dcm_adv_clk_main PHASE_SHIFT = 0;
INST dcm_adv_clk_main STARTUP_WAIT = FALSE;


# ROM Block Assignments
INST "rom_8x2k_hi_0/B8"  LOC = "RAMB16_X1Y2";
INST "rom_8x2k_lo_0/B8"  LOC = "RAMB16_X1Y1"; 

# RAM Block Assignments
INST "ram_8x512_hi_0/B8" LOC = "RAMB16_X1Y4";
INST "ram_8x512_lo_0/B8" LOC = "RAMB16_X1Y3"; 


#-----------------------------------------------------------------------------#
# Clock Sources                                                               #
#-----------------------------------------------------------------------------#

NET "CLK_50MHz"   LOC = "T9"     |     IOSTANDARD = LVCMOS33 ;   // Input
NET "CLK_SOCKET"  LOC = "D9"     |     IOSTANDARD = LVCMOS33 ;   // Input


#-----------------------------------------------------------------------------#
# Switches and LEDs                                                           #
#-----------------------------------------------------------------------------#

# Slide Switches
NET "SW7"         LOC = "K13"    |     IOSTANDARD = LVCMOS33 ;   // Input
NET "SW6"         LOC = "K14"    |     IOSTANDARD = LVCMOS33 ;   // Input
NET "SW5"         LOC = "J13"    |     IOSTANDARD = LVCMOS33 ;   // Input
NET "SW4"         LOC = "J14"    |     IOSTANDARD = LVCMOS33 ;   // Input
NET "SW3"         LOC = "H13"    |     IOSTANDARD = LVCMOS33 ;   // Input
NET "SW2"         LOC = "H14"    |     IOSTANDARD = LVCMOS33 ;   // Input
NET "SW1"         LOC = "G12"    |     IOSTANDARD = LVCMOS33 ;   // Input
NET "SW0"         LOC = "F12"    |     IOSTANDARD = LVCMOS33 ;   // Input

# Push Button Switches
NET "BTN3"        LOC = "L14"    |     IOSTANDARD = LVCMOS33 ;   // Input
NET "BTN2"        LOC = "L13"    |     IOSTANDARD = LVCMOS33 ;   // Input
NET "BTN1"        LOC = "M14"    |     IOSTANDARD = LVCMOS33 ;   // Input
NET "BTN0"        LOC = "M13"    |     IOSTANDARD = LVCMOS33 ;   // Input

# LEDs
NET "LED7"        LOC = "P11"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "LED6"        LOC = "P12"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "LED5"        LOC = "N12"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "LED4"        LOC = "P13"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "LED3"        LOC = "N14"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "LED2"        LOC = "L12"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "LED1"        LOC = "P14"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "LED0"        LOC = "K12"    |     IOSTANDARD = LVCMOS33 ;   // Output


#-----------------------------------------------------------------------------#
# Four-Sigit, Seven-Segment LED Display                                       #
#-----------------------------------------------------------------------------#

NET "SEG_A"       LOC = "E14"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SEG_B"       LOC = "G13"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SEG_C"       LOC = "N15"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SEG_D"       LOC = "P15"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SEG_E"       LOC = "R16"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SEG_F"       LOC = "F13"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SEG_G"       LOC = "N16"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SEG_DP"      LOC = "P16"    |     IOSTANDARD = LVCMOS33 ;   // Output

NET "SEG_AN0"     LOC = "D14"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SEG_AN1"     LOC = "G14"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SEG_AN2"     LOC = "F14"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SEG_AN3"     LOC = "E13"    |     IOSTANDARD = LVCMOS33 ;   // Output


#-----------------------------------------------------------------------------#
# RS-232 Port                                                                 #
#-----------------------------------------------------------------------------#

NET "UART_RXD"    LOC = "T13"    |     IOSTANDARD = LVCMOS33 ;   // Input
NET "UART_TXD"    LOC = "R13"    |     IOSTANDARD = LVCMOS33 ;   // Output

NET "UART_RXD_A"  LOC = "N10"    |     IOSTANDARD = LVCMOS33 ;   // Input
NET "UART_TXD_A"  LOC = "T14"    |     IOSTANDARD = LVCMOS33 ;   // Output


#-----------------------------------------------------------------------------#
# PS/2 Mouse/Keyboard Port                                                    #
#-----------------------------------------------------------------------------#

NET "PS2_D"       LOC = "M15"    |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "PS2_C"       LOC = "M16"    |     IOSTANDARD = LVCMOS33 ;   // Output


#-----------------------------------------------------------------------------#
# Fast, Asynchronous SRAM                                                     #
#-----------------------------------------------------------------------------#

# Address Bus Connections
NET "SRAM_A17"    LOC = "L3"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_A16"    LOC = "K5"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_A15"    LOC = "K3"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_A14"    LOC = "J3"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_A13"    LOC = "J4"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_A12"    LOC = "H4"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_A11"    LOC = "H3"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_A10"    LOC = "G5"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_A9"     LOC = "E4"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_A8"     LOC = "E3"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_A7"     LOC = "F4"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_A6"     LOC = "F3"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_A5"     LOC = "G4"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_A4"     LOC = "L4"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_A3"     LOC = "M3"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_A2"     LOC = "M4"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_A1"     LOC = "N3"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_A0"     LOC = "L5"     |     IOSTANDARD = LVCMOS33 ;   // Output


# Write enable and output enable control signals
NET "SRAM_OE"     LOC = "K4"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM_WE"     LOC = "G3"     |     IOSTANDARD = LVCMOS33 ;   // Output


# SRAM Data signals, chip enables, and byte enables
NET "SRAM0_IO15"  LOC = "R1"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM0_IO14"  LOC = "P1"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM0_IO13"  LOC = "L2"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM0_IO12"  LOC = "J2"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM0_IO11"  LOC = "H1"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM0_IO10"  LOC = "F2"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM0_IO9"   LOC = "P8"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM0_IO8"   LOC = "D3"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM0_IO7"   LOC = "B1"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM0_IO6"   LOC = "C1"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM0_IO5"   LOC = "C2"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM0_IO4"   LOC = "R5"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM0_IO3"   LOC = "T5"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM0_IO2"   LOC = "R6"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM0_IO1"   LOC = "T8"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM0_IO0"   LOC = "N7"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM0_CE1"   LOC = "P7"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM0_UB1"   LOC = "T4"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM0_LB1"   LOC = "P6"     |     IOSTANDARD = LVCMOS33 ;   // Output

NET "SRAM1_IO15"  LOC = "N1"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM1_IO14"  LOC = "M1"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM1_IO13"  LOC = "K2"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM1_IO12"  LOC = "C3"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM1_IO11"  LOC = "F5"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM1_IO10"  LOC = "G1"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM1_IO9"   LOC = "E2"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM1_IO8"   LOC = "D2"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM1_IO7"   LOC = "D1"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM1_IO6"   LOC = "E1"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM1_IO5"   LOC = "G2"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM1_IO4"   LOC = "J1"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM1_IO3"   LOC = "K1"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM1_IO2"   LOC = "M2"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM1_IO1"   LOC = "N2"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM1_IO0"   LOC = "P2"     |     IOSTANDARD = LVCMOS33 ;   // I/O
NET "SRAM1_CE2"   LOC = "N5"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM1_UB2"   LOC = "R4"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "SRAM1_LB2"   LOC = "P5"     |     IOSTANDARD = LVCMOS33 ;   // Output


#-----------------------------------------------------------------------------#
# VGA Port                                                                    #
#-----------------------------------------------------------------------------#

NET "VGA_R"       LOC = "R12"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "VGA_G"       LOC = "T12"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "VGA_B"       LOC = "R11"    |     IOSTANDARD = LVCMOS33 ;   // Output
NET "VGA_HS"      LOC = "R9"     |     IOSTANDARD = LVCMOS33 ;   // Output
NET "VGA_VS"      LOC = "T10"    |     IOSTANDARD = LVCMOS33 ;   // Output