OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [altivec-cell-1.c] - Rev 338

Compare with Previous | Blame | View Log

/* { dg-do compile { target powerpc*-*-* } } */
/* { dg-require-effective-target powerpc_altivec_ok } */
/* { dg-options "-maltivec" } */
 
/* Basic test for the new VMX intrinsics.  */
#include <altivec.h>
 
int f(vector int a, int b)
{
  return vec_extract (a, b);
}
short f1(vector short a, int b)
{
  return vec_extract (a, b);
}
vector short f2(vector short a, int b)
{
  return vec_insert (b, a, b);
}
vector float f3(vector float a, int b)
{
  return vec_insert (b, a, b);
}
 
float g(void);
 
vector float f4(float b, int t)
{
  return vec_promote (g(), t);
}
vector float f5(float b)
{
  return vec_splats (g());
}
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.