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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc2/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [altivec-cell-7.c] - Rev 384

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/* { dg-do compile  } */
/* { dg-require-effective-target powerpc_altivec_ok } */
/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */
/* { dg-final { scan-assembler-times "vor" 2 } } */
#include <altivec.h>
 
/* Make sure that lvlx and lvrx are not combined into one insn and
   we still get a vor. */
 
vector unsigned char
lvx_float (long off, float *p)
{
    vector unsigned char l, r;
 
    l = (vector unsigned char) vec_lvlx (off, p);
    r = (vector unsigned char) vec_lvrx (off, p);
    return vec_or(l, r);
}
 
vector unsigned char
lvxl_float (long off, float *p)
{
    vector unsigned char l, r;
 
    l = (vector unsigned char) vec_lvlxl (off, p);
    r = (vector unsigned char) vec_lvrxl (off, p);
    return vec_or(l, r);
}
 

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