URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc3/] [gcc/] [testsuite/] [gcc.c-torture/] [compile/] [20040109-1.c] - Rev 839
Go to most recent revision | Compare with Previous | Blame | View Log
/* PR target/13380. On m32r, the condition code register, (reg:SI 17), was replaced with a pseudo reg, which would cause an unrecognized insn. */ void foo (unsigned int a, unsigned int b) { if (a > b) { while (a) { switch (b) { default: a = 0; case 2: a = 0; case 1: a = 0; case 0: ; } } } }
Go to most recent revision | Compare with Previous | Blame | View Log