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https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc4/] [gcc/] [config/] [score/] [score.opt] - Rev 540
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; Options for the Sunnorth port of the compiler.
; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
meb
Target RejectNegative Report InverseMask(LITTLE_ENDIAN)
Generate big-endian code
mel
Target RejectNegative Report Mask(LITTLE_ENDIAN)
Generate little-endian code
mnhwloop
Target RejectNegative Report Mask(NHWLOOP)
Disable bcnz instruction
muls
Target RejectNegative Report Mask(ULS)
Enable unaligned load/store instruction
mscore5
Target RejectNegative Report Mask(SCORE5)
Support SCORE 5 ISA
mscore5u
Target RejectNegative Report Mask(SCORE5U)
Support SCORE 5U ISA
mscore7
Target RejectNegative Report Mask(SCORE7)
Support SCORE 7 ISA
mscore7d
Target RejectNegative Report Mask(SCORE7D)
Support SCORE 7D ISA
mscore3
Target RejectNegative Report Mask(SCORE3)
Support SCORE 3 ISA
mscore3d
Target RejectNegative Report Mask(SCORE3D)
Support SCORE 3d ISA
march=
Target RejectNegative Joined
Specify the name of the target architecture
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