URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
[/] [openrisc/] [tags/] [gnu-src/] [gdb-6.8/] [pre-binutils-2.20.1-sync/] [sim/] [testsuite/] [sim/] [arm/] [mov.cgs] - Rev 24
Go to most recent revision | Compare with Previous | Blame | View Log
# arm testcase for mov$cond${set-cc?} $rd,$imm12
# mach: unfinished
.include "testutils.inc"
start
.global mov_imm
mov_imm:
mov00 pc,0
pass
# arm testcase for mov$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}
# mach: unfinished
.include "testutils.inc"
start
.global mov_reg_imm_shift
mov_reg_imm_shift:
mov00 pc,pc,pc,lsl 0
pass
# arm testcase for mov$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}
# mach: unfinished
.include "testutils.inc"
start
.global mov_reg_reg_shift
mov_reg_reg_shift:
mov00 pc,pc,pc,lsl pc
pass
Go to most recent revision | Compare with Previous | Blame | View Log