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[/] [openrisc/] [tags/] [gnu-src/] [gdb-7.2/] [gdb-7.2-or32-1.0rc1/] [sim/] [testsuite/] [sim/] [frv/] [interrupts/] [insn_access_error.cgs] - Rev 341
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# frv testcase to generate insn_access_error interrupt
# mach: fr500 fr400
# sim: --memory-region 0xfeff0600,0x8000 --memory-region 0xfe800000,0x7f0040
.include "testutils.inc"
start
.global dsr
dsr:
and_spr_immed -4081,tbr ; clear tbr.tt
set_gr_spr tbr,gr17
inc_gr_immed 0x020,gr17 ; address of exception handler
set_bctrlr_0_0 gr17
set_spr_immed 128,lcr
set_psr_et 1
set_spr_addr handler,lr
set_gr_immed 0,gr16
set_gr_addr ok0,gr8
set_gr_addr 0xfeff0600,gr17
jmpl @(gr17,gr0) ; cause interrupt
ok0:
test_gr_immed 1,gr16
set_gr_addr ok1,gr8
set_gr_addr 0xfeff7ffc,gr17
jmpl @(gr17,gr0) ; cause interrupt
ok1:
test_gr_immed 2,gr16
set_gr_addr ok2,gr8
set_gr_addr 0xfe800000,gr17
jmpl @(gr17,gr0) ; cause interrupt
ok2:
test_gr_immed 3,gr16
set_gr_addr ok3,gr8
set_gr_addr 0xfefefffc,gr17
jmpl @(gr17,gr0) ; cause interrupt
ok3:
test_gr_immed 4,gr16
pass
handler:
; check interrupts
test_spr_immed 0x1,esfr1 ; esr0 is active
test_spr_gr epcr0,gr17
test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
test_spr_bits 0x003e,1,0x2,esr0 ; esr0.ec is set
test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set
addi gr16,1,gr16
movgs gr8,pcsr
rett 0
fail