URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [tags/] [gnu-src/] [gdb-7.2/] [gdb-7.2-or32-1.0rc3/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [tmiaph.cgs] - Rev 330
Go to most recent revision | Compare with Previous | Blame | View Log
# Intel(r) Wireless MMX(tm) technology testcase for TMIAPH
# mach: xscale
# as: -mcpu=xscale+iwmmxt
.include "testutils.inc"
start
.global tmiaph
tmiaph:
# Enable access to CoProcessors 0 & 1 before
# we attempt these instructions.
mvi_h_gr r1, 3
mcr p15, 0, r1, cr15, cr1, 0
# Test Multilply Accumulate
mvi_h_gr r0, 0x11223344
mvi_h_gr r1, 0x55667788
mvi_h_gr r2, 0x12345678
mvi_h_gr r3, 0x9abcdef0
tmcrr wr0, r0, r1
tmiaph wr0, r2, r3
tmrrc r0, r1, wr0
test_h_gr r0, 0xfec3f9f4
test_h_gr r1, 0x55667787
test_h_gr r2, 0x12345678
test_h_gr r3, 0x9abcdef0
pass
Go to most recent revision | Compare with Previous | Blame | View Log