Subversion Repositories openrisc

\initial {-}
\entry {\code {--cumulative}}{4}
\entry {\code {--debug-config}}{3}
\entry {\code {--enable-ethphy}}{2}
\entry {\code {--enable-mprofile}}{3}
\entry {\code {--enable-profile}}{3}
\entry {\code {--file}}{3}
\entry {\code {--filename}}{4}
\entry {\code {--generate}}{4}
\entry {\code {--group}}{4}
\entry {\code {--help}}{3}
\entry {\code {--help} (memory profiling utility)}{4}
\entry {\code {--help} (profiling utility)}{4}
\entry {\code {--interactive}}{3}
\entry {\code {--mode}}{4}
\entry {\code {--nosrv}}{3}
\entry {\code {--quiet}}{4}
\entry {\code {--srv}}{3}
\entry {\code {--version}}{3}
\entry {\code {--version} (memory profiling utility)}{4}
\entry {\code {--version} (profiling utility)}{4}
\entry {\code {-c}}{4}
\entry {\code {-d}}{3}
\entry {\code {-f}}{3, 4}
\entry {\code {-g}}{4}
\entry {\code {-h}}{3}
\entry {\code {-h} (memory profiling utility)}{4}
\entry {\code {-h} (profiling utility)}{4}
\entry {\code {-i}}{3}
\entry {\code {-m}}{4}
\entry {\code {-q}}{4}
\entry {\code {-v}}{3}
\entry {\code {-v} (memory profiling utility)}{4}
\entry {\code {-v} (profiling utility)}{4}
\initial {0}
\entry {0x00 UART VAPI sub-command (UART verification)}{30}
\entry {0x01 UART VAPI sub-command (UART verification)}{30}
\entry {0x02 UART VAPI sub-command (UART verification)}{30}
\entry {0x03 UART VAPI sub-command (UART verification)}{30}
\entry {0x04 UART VAPI sub-command (UART verification)}{30}
\initial {1}
\entry {\code {16550} (UART configuration)}{19}
\initial {A}
\entry {ATA/ATAPI configuration}{24}
\entry {ATA/ATAPI device configuration}{25}
\initial {B}
\entry {\code {base_vapi_id} (GPIO configuration - deprecated)}{22}
\entry {\code {baseaddr} (ATA/ATAPI configuration)}{24}
\entry {\code {baseaddr} (DMA configuration)}{20}
\entry {\code {baseaddr} (Ethernet configuration)}{20}
\entry {\code {baseaddr} (frame buffer configuration)}{23}
\entry {\code {baseaddr} (generic peripheral configuration)}{26}
\entry {\code {baseaddr} (GPIO configuration)}{21}
\entry {\code {baseaddr} (keyboard configuration)}{23}
\entry {\code {baseaddr} (memory configuration)}{13}
\entry {\code {baseaddr} (memory controller configuration)}{18}
\entry {\code {baseaddr} (UART configuration)}{18}
\entry {\code {baseaddr} (VGA configuration)}{22}
\entry {\code {blocksize} (cache configuration)}{15}
\entry {BPB configuration}{16}
\entry {branch prediction configuration}{16}
\entry {\code {break} (Interactive CLI)}{27}
\entry {breakpoint list (Interactive CLI)}{27}
\entry {breakpoint set/clear (Interactive CLI)}{27}
\entry {\code {breaks} (Interactive CLI)}{27}
\entry {\code {btic} (branch prediction configuration)}{16}
\entry {\code {byte_enabled} (generic peripheral configuration)}{26}
\initial {C}
\entry {cache configuration}{15}
\entry {\code {calling_convention} (CUC configuration)}{10}
\entry {\code {ce} (memory configuration)}{13}
\entry {\code {cfgr} (CPU configuration)}{11}
\entry {\code {channel} (UART configuration)}{18}
\entry {clear breakpoint (Interactive CLI)}{27}
\entry {\code {clkcycle} (simulator configuration)}{9}
\entry {\code {cm} (Interactive CLI)}{27}
\entry {command line for Or1ksim standalone use}{3}
\entry {\code {config}}{33}
\entry {\code {config.bpb}}{34}
\entry {\code {config.cpu}}{33}
\entry {\code {config.cuc}}{33}
\entry {\code {config.dc}}{33}
\entry {\code {config.debug}}{34}
\entry {\code {config.pic}}{34}
\entry {\code {config.pm}}{33}
\entry {\code {config.sim}}{33}
\entry {\code {config.vapi}}{33}
\entry {configuration dynamic structure}{34}
\entry {configuration file structure}{7}
\entry {configuration global structure}{33}
\entry {configuration info (Interactive CLI)}{28}
\entry {configuration of generic peripherals}{25}
\entry {configuration parameter setting (Interactive CLI)}{28}
\entry {configuring branch prediction}{16}
\entry {configuring data & instruction caches}{15}
\entry {configuring data & instruction MMUs}{14}
\entry {configuring DMA}{19}
\entry {configuring memory}{12}
\entry {configuring Or1ksim}{7}
\entry {configuring power management}{16}
\entry {configuring the ATA/ATAPI interfaces}{24}
\entry {configuring the behavior of Or1ksim}{8}
\entry {configuring the CPU}{11}
\entry {configuring the Custom Unit Compiler (CUC)}{10}
\entry {configuring the debug unit and interface to external debuggers}{17}
\entry {configuring the Ethernet interface}{20}
\entry {configuring the frame buffer}{22}
\entry {configuring the GPIO}{21}
\entry {configuring the interrupt controller}{15}
\entry {configuring the keyboard interface}{23}
\entry {configuring the memory controller}{17}
\entry {configuring the processor}{11}
\entry {configuring the PS2 interface}{23}
\entry {configuring the UART}{18}
\entry {configuring the Verification API (VAPI)}{9}
\entry {configuring the VGA interface}{22}
\entry {copying memory (Interactive CLI)}{27}
\entry {CPU configuration}{11}
\entry {CUC configuration}{10}
\entry {Custom Unit Compiler (Interactive CLI)}{29}
\entry {Custom Unit Compiler Configuration}{10}
\initial {D}
\entry {data cache configuration}{15}
\entry {data MMU configuration}{14}
\entry {DCGE (power management register)}{16}
\entry {\code {debug} (Interactive CLI)}{28, 29}
\entry {\code {debug} (simulator configuration)}{8}
\entry {debug channel toggle (Interactive CLI)}{28}
\entry {debug interface configuration}{17}
\entry {debug mode toggle (Interactive CLI)}{28}
\entry {debug unit configuration}{17}
\entry {Debug Unit verification (VAPI)}{30}
\entry {\code {delayr} (memory configuration)}{13}
\entry {\code {delayw} (memory configuration)}{14}
\entry {\code {dependstats} (CPU configuration)}{12}
\entry {\code {dev_id} (ATA/ATAPI configuration)}{24}
\entry {disassemble (Interactive CLI)}{27}
\entry {disc interface configuration}{24}
\entry {disc interface device configuration}{25}
\entry {display interface configuration}{22}
\entry {displaying memory (Interactive CLI)}{27}
\entry {displaying registers (Interactive CLI)}{27}
\entry {\code {dm} (Interactive CLI)}{27}
\entry {\code {dma} (Ethernet configuration)}{20}
\entry {DMA configuration}{19}
\entry {DMA verification (VAPI)}{30}
\entry {\code {dma_mode0_td} (ATA/ATAPI configuration)}{24}
\entry {\code {dma_mode0_teoc} (ATA/ATAPI configuration)}{24}
\entry {\code {dma_mode0_tm} (ATA/ATAPI configuration)}{24}
\entry {DME (power management register)}{16}
\entry {DMMU configuration}{14}
\entry {doze mode (power management register)}{16}
\entry {\code {dv} (Interactive CLI)}{28}
\entry {dynamic clock gating (power management register)}{16}
\entry {dynamic ports, use of}{10}
\initial {E}
\entry {\code {edge_trigger} (interrupt controller)}{16}
\entry {\code {enable_bursts} (CUC configuration)}{10}
\entry {\code {enabled} (ATA/ATAPI configuration)}{24}
\entry {\code {enabled} (branch prediction configuration)}{16}
\entry {\code {enabled} (cache configuration)}{15}
\entry {\code {enabled} (debug interface configuration)}{17}
\entry {\code {enabled} (DMA configuration)}{20}
\entry {\code {enabled} (Ethernet configuration)}{20}
\entry {\code {enabled} (frame buffer configuration)}{22}
\entry {\code {enabled} (generic peripheral configuration)}{26}
\entry {\code {enabled} (GPIO configuration)}{21}
\entry {\code {enabled} (interrupt controller)}{16}
\entry {\code {enabled} (keyboard configuration)}{23}
\entry {\code {enabled} (memory controller configuration)}{18}
\entry {\code {enabled} (MMU configuration)}{14}
\entry {\code {enabled} (power management configuration)}{16}
\entry {\code {enabled} (UART configuration)}{18}
\entry {\code {enabled} (verification API configuration)}{10}
\entry {\code {enabled} (VGA configuration)}{22}
\entry {enabling Ethernet via socket}{2}
\entry {\code {entrysize} (MMU configuration)}{14}
\entry {\code {ETH_VAPI_CTRL} (Ethernet verification)}{31}
\entry {\code {ETH_VAPI_DATA} (Ethernet verification)}{31}
\entry {Ethernet configuration}{20}
\entry {Ethernet verification (VAPI)}{30}
\entry {Ethernet via socket, enabling}{2}
\entry {\code {exe_log} (simulator configuration)}{9}
\entry {\code {exe_log_end} (simulator configuration)}{9}
\entry {\code {exe_log_file} (simulator configuration)}{9}
\entry {\code {exe_log_fn} (simulator configuration - deprecated)}{9}
\entry {\code {exe_log_marker} (simulator configuration)}{9}
\entry {\code {exe_log_start} (simulator configuration)}{9}
\entry {\code {exe_log_type} (simulator configuration)}{9}
\entry {\code {exe_log_type=default} (simulator configuration)}{9}
\entry {\code {exe_log_type=hardware} (simulator configuration)}{9}
\entry {\code {exe_log_type=simple} (simulator configuration)}{9}
\entry {\code {exe_log_type=software} (simulator configuration)}{9}
\entry {executing code (Interactive CLI)}{27}
\entry {execution history (Interactive CLI)}{27}
\initial {F}
\entry {\code {file} (ATA/ATAPI device configuration)}{25}
\entry {\code {file} (keyboard configuration)}{23}
\entry {\code {filename} (frame buffer configuration - deprecated)}{23}
\entry {\code {filename} (VGA configuration - deprecated)}{22}
\entry {\code {firmware} (ATA/ATAPI device configuration)}{25}
\entry {frame buffer configuration}{22}
\initial {G}
\entry {\code {gdb_enabled} (debug interface configuration)}{17}
\entry {generic peripheral configuration}{25}
\entry {GPIO configuration}{21}
\entry {GPIO verification (VAPI)}{31}
\entry {\code {GPIO_VAPI_AUX} (GPIO verification)}{31}
\entry {\code {GPIO_VAPI_CLOCK} (GPIO verification)}{31}
\entry {\code {GPIO_VAPI_CTRL} (GPIO verification)}{31}
\entry {\code {GPIO_VAPI_DATA} (GPIO verification)}{31}
\entry {\code {GPIO_VAPI_INTE} (GPIO verification)}{31}
\entry {\code {GPIO_VAPI_PTRIG} (GPIO verification)}{31}
\entry {\code {GPIO_VAPI_RGPIO} (GPIO verification)}{31}
\initial {H}
\entry {\code {hazards} (CPU configuration)}{12}
\entry {\code {heads} (ATA/ATAPI device configuration)}{25}
\entry {\code {help} (Interactive CLI)}{29}
\entry {hexadecimal memory dump (Interactive CLI)}{28}
\entry {\code {hide_device_id} (verification API configuration)}{10}
\entry {\code {hist} (Interactive CLI)}{27}
\entry {\code {history} (simulator configuration)}{8}
\entry {history of execution (Interactive CLI)}{27}
\entry {\code {hitdelay} (branch prediction configuration)}{16}
\entry {\code {hitdelay} (instruction cache configuration)}{15}
\entry {\code {hitdelay} (MMU configuration)}{14}
\entry {\code {hw_enabled} (generic peripheral configuration)}{26}
\initial {I}
\entry {IMMU configuration}{14}
\entry {\code {index} (memory controller configuration)}{18}
\entry {\code {info} (Interactive CLI)}{28}
\entry {installing Or1ksim}{2}
\entry {instruction cache configuration}{15}
\entry {instruction MMU configuration}{14}
\entry {instruction profiling for Or1ksim}{3}
\entry {instruction profiling utility (Interactive CLI)}{29}
\entry {internal debugging}{34}
\entry {interrupt controller configuration}{15}
\entry {\code {irq} (ATA/ATAPI configuration)}{24}
\entry {\code {irq} (DMA configuration)}{20}
\entry {\code {irq} (GPIO configuration)}{22}
\entry {\code {irq} (keyboard configuration)}{23}
\entry {\code {irq} (UART configuration)}{19}
\entry {\code {irq} (VGA configuration)}{22}
\initial {J}
\entry {\code {jitter} (UART configuration)}{19}
\initial {K}
\entry {keyboard configuration}{23}
\initial {L}
\entry {library version of Or1ksim}{5}
\entry {license for Or1ksim}{35}
\entry {list breakpoints (Interactive CLI)}{27}
\entry {\code {load_hitdelay} (data cache configuration)}{15}
\entry {\code {load_missdelay} (data cache configuration)}{15}
\entry {\code {log} (memory configuration)}{14}
\entry {\code {log_enabled} (verification API configuration)}{10}
\entry {\code {long}}{5}
\initial {M}
\entry {\code {mc} (memory configuration)}{13}
\entry {memory configuration}{12}
\entry {memory controller configuration}{17}
\entry {memory copying (Interactive CLI)}{27}
\entry {memory display (Interactive CLI)}{27}
\entry {memory dump, hexadecimal (Interactive CLI)}{28}
\entry {memory dump, Verilog (Interactive CLI)}{28}
\entry {memory patching (Interactive CLI)}{27}
\entry {memory profiling end address}{4}
\entry {memory profiling start address}{4}
\entry {memory profiling utility (Interactive CLI)}{29}
\entry {memory profiling version of Or1ksim}{4}
\entry {\code {memory_order} (CUC configuration)}{10}
\entry {\code {memory_order=exact} (CUC configuration)}{10}
\entry {\code {memory_order=none} (CUC configuration)}{10}
\entry {\code {memory_order=strong} (CUC configuration)}{10}
\entry {\code {memory_order=weak} (CUC configuration)}{10}
\entry {\code {missdelay} (branch prediction configuration)}{17}
\entry {\code {missdelay} (instruction cache configuration)}{15}
\entry {\code {missdelay} (MMU configuration)}{14}
\entry {MMU configuration}{14}
\entry {\code {mprof_file} (simulator configuration)}{8}
\entry {\code {mprof_fn} (simulator configuration - deprecated)}{8}
\entry {\code {mprofile} (Interactive CLI)}{29}
\entry {\code {mprofile} (simulator configuration)}{8}
\entry {\code {mwdma} (ATA/ATAPI device configuration)}{25}
\initial {N}
\entry {\code {name} (generic peripheral configuration)}{26}
\entry {\code {name} (memory configuration)}{13}
\entry {\code {no_multicycle} (CUC configuration)}{11}
\entry {\code {nsets} (cache configuration)}{15}
\entry {\code {nsets} (MMU configuration)}{14}
\entry {\code {nways} (cache configuration)}{15}
\entry {\code {nways} (MMU configuration)}{14}
\initial {O}
\entry {\code {or1ksim_get_time_period}}{5}
\entry {\code {or1ksim_init}}{5}
\entry {\code {or1ksim_interrupt}}{5}
\entry {\code {or1ksim_is_le}}{5}
\entry {\code {or1ksim_reset_duration}}{5}
\entry {\code {or1ksim_run}}{5}
\entry {\code {or1ksim_set_time_point}}{5}
\entry {output rediretion}{34}
\initial {P}
\entry {\code {packet} (ATA/ATAPI device configuration)}{25}
\entry {\code {pagesize} (MMU configuration)}{14}
\entry {patching memory (Interactive CLI)}{27}
\entry {patching registers (Interactive CLI)}{27}
\entry {patching the program counter (Interactive CLI)}{27}
\entry {\code {pattern} (memory configuration)}{13}
\entry {\code {pc} (Interactive CLI)}{27}
\entry {PIC configuration}{15}
\entry {\code {pio} (ATA/ATAPI device configuration)}{25}
\entry {\code {pio_mode0_t1} (ATA/ATAPI configuration)}{24}
\entry {\code {pio_mode0_t2} (ATA/ATAPI configuration)}{24}
\entry {\code {pio_mode0_t4} (ATA/ATAPI configuration)}{24}
\entry {\code {pio_mode0_teoc} (ATA/ATAPI configuration)}{24}
\entry {\code {pm} (Interactive CLI)}{27}
\entry {PMR - DGCE}{16}
\entry {PMR - DME}{16}
\entry {PMR - SDF}{16}
\entry {PMR - SME}{16}
\entry {PMR - SUME}{16}
\entry {PMU configuration}{16}
\entry {\code {poc} (memory controller configuration)}{18}
\entry {port range for TCP/IP}{10}
\entry {power management configuration}{16}
\entry {power management register, DGCE}{16}
\entry {power management register, DME}{16}
\entry {power management register, SDF}{16}
\entry {power management register, SME}{16}
\entry {power management register, SUME}{16}
\entry {\code {pr} (Interactive CLI)}{27}
\entry {private ports, use of}{10}
\entry {processor configuration}{11}
\entry {processor stall (Interactive CLI)}{27}
\entry {\code {prof_file} (simulator configuration)}{8}
\entry {\code {prof_fn} (simulator configuration - deprecated)}{8}
\entry {\code {profile} (simulator configuration)}{8}
\entry {profiling for Or1ksim}{3}
\entry {profiling utility (Interactive CLI)}{29}
\entry {program counter patching (Interactive CLI)}{27}
\entry {programmable interrupt controller configuration}{15}
\entry {PS2 configuration}{23}
\initial {Q}
\entry {\code {q} (Interactive CLI)}{27}
\entry {quitting (Interactive CLI)}{27}
\initial {R}
\entry {\code {r} (Interactive CLI)}{27}
\entry {\code {random_seed} (memory configuration)}{12}
\entry {\code {refresh_rate} (frame buffer configuration)}{23}
\entry {\code {refresh_rate} (VGA configuration)}{22}
\entry {\code {reg_sim_reset}}{34}
\entry {register display (Interactive CLI)}{27}
\entry {register patching (Interactive CLI)}{27}
\entry {\code {reset} (Interactive CLI)}{27}
\entry {reset hooks}{34}
\entry {reset the simulator (Interactive CLI)}{27}
\entry {\code {rev} (ATA/ATAPI configuration)}{24}
\entry {\code {rev} (CPU configuration)}{11}
\entry {\code {rtx_type} (Ethernet configuration)}{21}
\entry {\code {run} (Interactive CLI)}{27}
\entry {running code (Interactive CLI)}{27}
\entry {running Or1ksim}{3}
\entry {\code {runtime}}{34}
\entry {runtime global structure}{34}
\entry {\code {runtime.cpu}}{34}
\entry {\code {runtime.cpu.fout}}{34}
\entry {\code {runtime.cuc}}{34}
\entry {\code {runtime.vapi}}{34}
\entry {\code {rx_channel} (Ethernet configuration)}{21}
\entry {\code {rxfile} (Ethernet configuration)}{21}
\initial {S}
\entry {\code {sbp_bf_fwd} (branch prediction configuration)}{16}
\entry {\code {sbp_bnf_fwd} (branch prediction configuration)}{16}
\entry {\code {sbuf_len} (CPU configuration)}{12}
\entry {SDF (power management register)}{16}
\entry {\code {section ata}}{24}
\entry {\code {section bpb}}{16}
\entry {\code {section cpio}}{21}
\entry {\code {section cpu}}{11}
\entry {\code {section cuc}}{10}
\entry {\code {section dc}}{15}
\entry {\code {section debug}}{17}
\entry {\code {section dma}}{19}
\entry {\code {section dmmu}}{14}
\entry {\code {section ethernet}}{20}
\entry {\code {section fb}}{22}
\entry {\code {section generic}}{25}
\entry {\code {section ic}}{15}
\entry {\code {section immu}}{14}
\entry {\code {section kb}}{23}
\entry {\code {section mc}}{17}
\entry {\code {section memory}}{12}
\entry {\code {section pic}}{15}
\entry {\code {section pmu}}{16}
\entry {\code {section sim}}{8}
\entry {\code {section uart}}{18}
\entry {\code {section vapi}}{9}
\entry {\code {section vga}}{22}
\entry {\code {sections}}{34}
\entry {\code {sectors} (ATA/ATAPI device configuration)}{25}
\entry {\code {server_port} (debug interface configuration)}{17}
\entry {\code {server_port} (verification API configuration)}{10}
\entry {\code {set} (Interactive CLI)}{28}
\entry {set breakpoint (Interactive CLI)}{27}
\entry {\code {setdbch} (Interactive CLI)}{28}
\entry {simulator configuration}{8}
\entry {simulator configuration info (Interactive CLI)}{28}
\entry {simulator reset (Interactive CLI)}{27}
\entry {simulator statistics (Interactive CLI)}{28}
\entry {\code {size} (ATA/ATAPI device configuration)}{25}
\entry {\code {size} (generic peripheral configuration)}{26}
\entry {\code {size} (memory configuration)}{13}
\entry {sleep mode (power management register)}{16}
\entry {slow down factor (power management register)}{16}
\entry {SME (power management register)}{16}
\entry {\code {sockif} (Ethernet configuration)}{21}
\entry {\code {sr} (CPU configuration)}{11}
\entry {\code {stall} (Interactive CLI)}{27}
\entry {stall the processor (Interactive CLI)}{27}
\entry {statistics, simulation (Interactive CLI)}{28}
\entry {\code {stats} (Interactive CLI)}{28}
\entry {stepping code (Interactive CLI)}{27}
\entry {\code {store_hitdelay} (data cache configuration)}{15}
\entry {\code {store_missdelay} (data cache configuration)}{15}
\entry {SUME (power management register)}{16}
\entry {\code {superscalar} (CPU configuration)}{11}
\entry {suspend mode (power management register)}{16}
\initial {T}
\entry {\code {t} (Interactive CLI)}{27}
\entry {TCP/IP port range}{10}
\entry {TCP/IP port range for \code {or1ksim} service}{17}
\entry {\code {timings_file} (CUC configuration)}{11}
\entry {\code {timings_fn} (CUC configuration - deprecated)}{11}
\entry {toggle breakpoint (Interactive CLI)}{27}
\entry {toggle debug channels (Interactive CLI)}{28}
\entry {toggle debug mode (Interactive CLI)}{28}
\entry {\code {tx_channel} (Ethernet configuration)}{21}
\entry {\code {txfile} (Ethernet configuration)}{21}
\entry {\code {txfile} (frame buffer configuration)}{23}
\entry {\code {txfile} (VGA configuration)}{22}
\entry {\code {type} (ATA/ATAPI device configuration)}{25}
\entry {\code {type} (memory configuration)}{12}
\entry {\code {type=pattern} (memory configuration)}{12}
\entry {\code {type=random} (memory configuration)}{12}
\entry {\code {type=unknown} (memory configuration)}{12}
\entry {\code {type=zero} (memory configuration)}{12}
\initial {U}
\entry {UART configuration}{18}
\entry {UART I/O from/to a physical serial port}{19}
\entry {UART I/O from/to an \command {xterm}}{19}
\entry {UART I/O from/to files}{19}
\entry {UART I/O from/to open file descriptors}{19}
\entry {UART I/O from/to TCP/IP}{19}
\entry {UART verification (VAPI)}{30}
\entry {\code {upr} (CPU configuration)}{11}
\entry {\code {ustates} (cache configuration)}{15}
\entry {\code {ustates} (MMU configuration)}{14}
\initial {V}
\entry {VAPI configuration}{9}
\entry {VAPI for Debug Unit}{30}
\entry {VAPI for DMA}{30}
\entry {VAPI for Ethernet}{30}
\entry {VAPI for GPIO}{31}
\entry {VAPI for UART}{30}
\entry {\code {vapi_id} (debug interface configuration)}{17}
\entry {\code {vapi_id} (DMA configuration)}{20, 21}
\entry {\code {vapi_id} (GPIO configuration)}{22}
\entry {\code {vapi_id} (UART configuration)}{19}
\entry {\code {vapi_log_file} (verification API configuration)}{10}
\entry {\code {vapi_log_fn} (verification API configuration - deprecated)}{10}
\entry {\code {ver} (CPU configuration)}{11}
\entry {\code {verbose} (simulator configuration)}{8}
\entry {Verification API configuration}{9}
\entry {Verilog memory dump (Interactive CLI)}{28}
\entry {VGA configuration}{22}
\initial {W}
\entry {\code {word_enabled} (generic peripheral configuration)}{26}