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[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.3.0/] [build/] [doc/] [or1ksim.toc] - Rev 846
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@unnchapentry{Scope of this Document}{10001}{Top}{1}
@numchapentry{Installation}{1}{Installation}{2}
@numchapentry{Usage}{2}{Usage}{3}
@numsecentry{Standalone Simulator}{2.1}{Standalone Simulator}{3}
@numsecentry{Profiling Utility}{2.2}{Profiling Utility}{3}
@numsecentry{Memory Profiling Utility}{2.3}{Memory Profiling Utility}{4}
@numsecentry{Simulator Library}{2.4}{Simulator Library}{5}
@numchapentry{Configuration}{3}{Configuration}{7}
@numsecentry{Configuration File Format}{3.1}{Configuration File Format}{7}
@numsubsecentry{Configuration File Preprocessing}{3.1.1}{Configuration File Preprocessing}{7}
@numsubsecentry{Configuration File Syntax}{3.1.2}{Configuration File Syntax}{7}
@numsecentry{Simulator Configuration}{3.2}{Simulator Configuration}{8}
@numsubsecentry{Simulator Behavior}{3.2.1}{Simulator Behavior}{8}
@numsubsecentry{Verification API (VAPI) Configuration}{3.2.2}{Verification API Configuration}{9}
@numsubsecentry{Custom Unit Compiler (CUC) Configuration}{3.2.3}{CUC Configuration}{10}
@numsecentry{Configuring the OpenRISC Architectural Components}{3.3}{Core OpenRISC Configuration}{11}
@numsubsecentry{CPU Configuration}{3.3.1}{CPU Configuration}{11}
@numsubsecentry{Memory Configuration}{3.3.2}{Memory Configuration}{12}
@numsubsecentry{Memory Management Configuration}{3.3.3}{Memory Management Configuration}{14}
@numsubsecentry{Cache Configuration}{3.3.4}{Cache Configuration}{15}
@numsubsecentry{Interrupt Configuration}{3.3.5}{Interrupt Configuration}{15}
@numsubsecentry{Power Management Configuration}{3.3.6}{Power Management Configuration}{16}
@numsubsecentry{Branch Prediction Configuration}{3.3.7}{Branch Prediction Configuration}{16}
@numsubsecentry{Debug Interface Configuration}{3.3.8}{Debug Interface Configuration}{17}
@numsecentry{Configuring Memory Mapped Peripherals}{3.4}{Peripheral Configuration}{17}
@numsubsecentry{Memory Controller Configuration}{3.4.1}{Memory Controller Configuration}{17}
@numsubsecentry{UART Configuration}{3.4.2}{UART Configuration}{18}
@numsubsecentry{DMA Configuration}{3.4.3}{DMA Configuration}{19}
@numsubsecentry{Ethernet Configuration}{3.4.4}{Ethernet Configuration}{20}
@numsubsecentry{GPIO Configuration}{3.4.5}{GPIO Configuration}{21}
@numsubsecentry{Display Interface Configuration}{3.4.6}{Display Interface Configuration}{22}
@numsubsecentry{Frame Buffer Configuration}{3.4.7}{Frame Buffer Configuration}{22}
@numsubsecentry{Keyboard Configuration (PS2)}{3.4.8}{Keyboard Configuration}{23}
@numsubsecentry{Disc Interface Configuration}{3.4.9}{Disc Interface Configuration}{24}
@numsubsubsecentry{ATA/ATAPI Device Configuration}{3.4.9.1}{}{25}
@numsubsecentry{Generic Peripheral Configuration}{3.4.10}{Generic Peripheral Configuration}{25}
@numchapentry{Interactive Command Line}{4}{Interactive Command Line}{27}
@numchapentry{Verification API (VAPI)}{5}{Verification API}{30}
@numchapentry{A Guide to Or1ksim Internals}{6}{Code Internals}{32}
@numsecentry{Coding Conventions for Or1ksim}{6.1}{Coding Conventions}{32}
@numsecentry{Global Data Structures}{6.2}{Global Data Structures}{33}
@numsecentry{Concepts}{6.3}{Concepts}{34}
@numsecentry{Internal Debugging}{6.4}{Internal Debugging}{34}
@numchapentry{GNU Free Documentation License}{7}{GNU Free Documentation License}{35}
@unnchapentry{Index}{10002}{Index}{42}
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