URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.3.0/] [testbench/] [mmu.cfg] - Rev 464
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section memory
/*random_seed = 12345
type = random*/
pattern = 0x00
type = unknown /* Fastest */
name = "RAM"
ce = 1
baseaddr = 0x00000000
size = 0x00200000
delayr = 1
delayw = 2
end
section memory
/*random_seed = 12345
type = random*/
pattern = 0x00
type = unknown /* Fastest */
name = "FLASH"
ce = 0
baseaddr = 0xf0000000
size = 0x00200000
delayr = 10
delayw = -1
end
section immu
enabled = 1
nsets = 64
nways = 1
ustates = 2
pagesize = 8192
end
section dmmu
enabled = 1
nsets = 64
nways = 1
ustates = 2
pagesize = 8192
end
section ic
enabled = 1
nsets = 256
nways = 1
ustates = 2
blocksize = 16
end
section dc
enabled = 1
nsets = 256
nways = 1
ustates = 2
blocksize = 16
end
section sim
/* verbose = 1 */
debug = 0
profile = 0
prof_fn = "sim.profile"
history = 1
/* iprompt = 0 */
exe_log = 0
exe_log_fn = "executed.log"
end
section mc
enabled = 1
baseaddr = 0x93000000
POC = 0x00000008 /* Power on configuration register */
end
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