OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [doc/] [ORPmref.tex] - Rev 248

Go to most recent revision | Compare with Previous | Blame | View Log

\documentstyle[10pt]{letter}
\topmargin -2cm
\textwidth 19cm
\textheight 28cm
\hoffset -2cm
 
\begin{document}
 
\newcommand{\addorpcmd}[3]{{\small\tt#1}\hfil&{\small\tt #2}\hfil&{\small\rm#3}\hfil\\}
\thispagestyle{empty}
\begin{centering}
\noindent{\large{\bf ORP Monitor Quick Reference}\\\ \\}
\noindent
\begin{tabular}{lp{5cm}p{7cm}}\hline
{\bf Command} & {\bf Parameters} & {\bf Description} \\ \hline\hline
\addorpcmd{help}{}{shows help}
\addorpcmd{dm}{$<$start addr$>$ [$<$end addr$>$]}{display 32-bit memory location(s)}
\addorpcmd{pm}{$<$addr$>$ [$<$stop\_addr$>$] $<$value$>$}{patch 32-bit memory location(s)}
\addorpcmd{copy}{[$<$dst\_addr$>$ [$<$src\_addr [$<$length$>$]]]}{copy memory}
\addorpcmd{mfspr}{$<$spr\_addr$>$}{show SPR}
\addorpcmd{mtspr}{$<$spr\_addr$>$ $<$value$>$}{set SPR}
\hline
\addorpcmd{crc}{[$<$src\_addr$>$ [$<$length$>$ [$<$init\_crc$>$]]]}{calculates a 32-bit CRC on specified memory region}
\addorpcmd{tftp}{[$<$file$>$ [$<$srv\_ip$>$ [$<$src\_addr$>$]]]}{TFTP download}
\addorpcmd{ic\_enable}{}{enable instruction cache}
\addorpcmd{ic\_disable}{}{disable instruction cache}
\addorpcmd{dc\_enable}{}{enable data cache}
\addorpcmd{dc\_disable}{}{disable data cache}
\addorpcmd{ram\_test}{$<$start\_addr$>$ $<$stop\_addr$>$ [$<$test\_no$>$]}{run a simple RAM test}
\addorpcmd{dhry}{[$<$num\_runs$>$]}{run dhrystone}
\hline
\addorpcmd{globals}{}{show globals and their current values}
\addorpcmd{src\_addr}{$<$value$>$}{sets global parameter source address}
\addorpcmd{dst\_addr}{$<$value$>$}{sets global parameter destination address}
\addorpcmd{start\_addr}{$<$value$>$}{sets global parameter start address}
\addorpcmd{length}{$<$value$>$}{sets global parameter {\tt length}}
\addorpcmd{erase\_method}{$<$value$>$ $<$value$>$ $<$value$>$}{sets flash erase method global parameter (0=do~not~erase, 1=fully, 2=as~needed)}
\addorpcmd{set\_dest\_addr}{$<$addrhi$>$ $<$addrmid$>$ $<$addrlo$>$}{set destination address global parameter}
\addorpcmd{ip}{$<$value$>$ $<$value$>$ $<$value$>$}{sets {\tt ip} address global parameter}
\addorpcmd{srv\_ip}{$<$value$>$ $<$value$>$ $<$value$>$}{sets server ip address global parameter}
\hline
\addorpcmd{eth\_init}{}{init ethernet}
\addorpcmd{show\_txbd}{[$<$start BD$>$] [$<$max$>$]}{show Tx buffer desc}
\addorpcmd{show\_rxbd}{[$<$start BD$>$] [$<$max$>$]}{show Rx buffer desc}
\addorpcmd{send\_packet}{$<$length$>$ [$<$start data$>$] [$<$num\_of\_packets$>$]}{create and send packet(s)}
\addorpcmd{init\_txbd\_pool}{$<$max$>$}{initialize Tx buffer descriptors}
\addorpcmd{init\_rxbd\_pool}{$<$max$>$}{initialize Rx buffer descriptors}
\addorpcmd{show\_phy\_reg}{[$<$start\_addr$>$] [$<$end addr$>$]}{show PHY registers}
\addorpcmd{set\_phy\_reg}{$<$addr$>$ $<$value$>$}{set PHY register}
\addorpcmd{show\_mac\_regs}{}{show all MAC registers}
\addorpcmd{eth\_int\_enable}{}{enable ethernet interrupt}
\addorpcmd{show\_rx\_buffs}{[$<$show\_all$>$]}{show receive buffers (optional argument will also show empty buffers)}
\addorpcmd{show\_tx\_buffs}{}{show transmit buffers}
\hline
\addorpcmd{crt\_enable}{}{enables CRT}
\addorpcmd{crt\_disable}{}{disables CRT}
\addorpcmd{crt\_test}{}{enables CRT and displays some test patterns}
\addorpcmd{camera\_enable}{}{enables camera}
\addorpcmd{camera\_disable}{}{disables camera}
\hline
\end{tabular}
\end{centering}
\end{document}
 
 

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.