URL
                    https://opencores.org/ocsvn/openrisc/openrisc/trunk
                
            Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [mep/] [mep-c5.cpu] - Rev 709
Compare with Previous | Blame | View Log
; Toshiba MeP C5 Core description. -*- scheme -*-; Copyright (C) 2009; Free Software Foundation, Inc.; Contributed by Red Hat, Inc.;; This file is part of GCC.;; GCC is free software; you can redistribute it and/or modify it under; the terms of the GNU General Public License as published by the Free; Software Foundation; either version 3, or (at your option) any later; version.;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY; WARRANTY; without even the implied warranty of MERCHANTABILITY or; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License; for more details.;; You should have received a copy of the GNU General Public License; along with GCC; see the file COPYING3. If not see; <http://www.gnu.org/licenses/>.(dnf f-c5n4 "extended field" (all-mep-core-isas) 16 4)(dnf f-c5n5 "extended field" (all-mep-core-isas) 20 4)(dnf f-c5n6 "extended field" (all-mep-core-isas) 24 4)(dnf f-c5n7 "extended field" (all-mep-core-isas) 28 4)(dnf f-rl5 "register l c5" (all-mep-core-isas) 20 4)(df f-12s20 "extended field" (all-mep-core-isas) 20 12 INT #f #f)(dnop rl5 "register Rl c5" (all-mep-core-isas) h-gpr f-rl5)(dnop cdisp12 "copro addend (12 bits)" (all-mep-core-isas) h-sint f-12s20)(dnci stcb_r "store in control bus space" (VOLATILE (MACH c5))"stcb $rn,($rma)"(+ MAJ_7 rn rma (f-sub4 12))(c-call VOID "do_stcb" rn (and rma #xffff))((mep (unit u-use-gpr (in usereg rn))(unit u-use-gpr (in usereg rma))(unit u-exec)(unit u-stcb))))(dnci ldcb_r "load from control bus space" (VOLATILE (MACH c5) (LATENCY 3))"ldcb $rn,($rma)"(+ MAJ_7 rn rma (f-sub4 13))(set rn (c-call SI "do_ldcb" (and rma #xffff)))((mep (unit u-use-gpr (in usereg rma))(unit u-ldcb)(unit u-exec)(unit u-ldcb-gpr (out loadreg rn)))))(dnci pref "cache prefetch" ((MACH c5) VOLATILE)"pref $cimm4,($rma)"(+ MAJ_7 cimm4 rma (f-sub4 5))(sequence ()(c-call VOID "check_option_dcache" pc)(c-call VOID "do_cache_prefetch" cimm4 rma pc))((mep (unit u-use-gpr (in usereg rma))(unit u-exec))))(dnci prefd "cache prefetch" ((MACH c5) VOLATILE)"pref $cimm4,$sdisp16($rma)"(+ MAJ_15 cimm4 rma (f-sub4 3) sdisp16)(sequence ()(c-call VOID "check_option_dcache" pc)(c-call VOID "do_cache_prefetch" cimm4 (add INT rma (ext SI sdisp16)) pc))((mep (unit u-use-gpr (in usereg rma))(unit u-exec))))(dnci casb3 "compare and swap byte 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)"casb3 $rl5,$rn,($rm)"(+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x0))(sequence ()(c-call VOID "do_casb3" (index-of rl5) rn rm pc)(set rl5 rl5))((mep (unit u-use-gpr (in usereg rl5))(unit u-load-gpr (out loadreg rl5))(unit u-exec))))(dnci cash3 "compare and swap halfword 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)"cash3 $rl5,$rn,($rm)"(+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x1))(sequence ()(c-call VOID "do_cash3" (index-of rl5) rn rm pc)(set rl5 rl5))((mep (unit u-use-gpr (in usereg rl5))(unit u-load-gpr (out loadreg rl5))(unit u-exec))))(dnci casw3 "compare and swap word 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN)"casw3 $rl5,$rn,($rm)"(+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x2))(sequence ()(c-call VOID "do_casw3" (index-of rl5) rn rm pc)(set rl5 rl5))((mep (unit u-use-gpr (in usereg rl5))(unit u-load-gpr (out loadreg rl5))(unit u-exec))))(dnci sbcp "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))"sbcp $crn,$cdisp12($rma)"(+ MAJ_15 crn rma (f-sub4 6) (f-ext4 0) cdisp12)(sequence ()(c-call "check_option_cp" pc)(c-call VOID "check_write_to_text" (add rma (ext SI cdisp12)))(set (mem QI (add rma (ext SI cdisp12))) (and crn #xff)))((mep (unit u-use-gpr (in usereg rma))(unit u-exec))))(dnci lbcp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))"lbcp $crn,$cdisp12($rma)"(+ MAJ_15 crn rma (f-sub4 6) (f-ext4 4) cdisp12)(sequence ()(c-call "check_option_cp" pc)(set crn (ext SI (mem QI (add rma (ext SI cdisp12))))))((mep (unit u-use-gpr (in usereg rma))(unit u-exec))))(dnci lbucp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))"lbucp $crn,$cdisp12($rma)"(+ MAJ_15 crn rma (f-sub4 6) (f-ext4 12) cdisp12)(sequence ()(c-call "check_option_cp" pc)(set crn (zext SI (mem QI (add rma (ext SI cdisp12))))))((mep (unit u-use-gpr (in usereg rma))(unit u-exec))))(dnci shcp "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))"shcp $crn,$cdisp12($rma)"(+ MAJ_15 crn rma (f-sub4 6) (f-ext4 1) cdisp12)(sequence ()(c-call "check_option_cp" pc)(c-call VOID "check_write_to_text" (add rma (ext SI cdisp12)))(set (mem HI (add rma (ext SI cdisp12))) (and crn #xffff)))((mep (unit u-use-gpr (in usereg rma))(unit u-exec))))(dnci lhcp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))"lhcp $crn,$cdisp12($rma)"(+ MAJ_15 crn rma (f-sub4 6) (f-ext4 5) cdisp12)(sequence ()(c-call "check_option_cp" pc)(set crn (ext SI (mem HI (add rma (ext SI cdisp12))))))((mep (unit u-use-gpr (in usereg rma))(unit u-exec))))(dnci lhucp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5))"lhucp $crn,$cdisp12($rma)"(+ MAJ_15 crn rma (f-sub4 6) (f-ext4 13) cdisp12)(sequence ()(c-call "check_option_cp" pc)(set crn (zext SI (mem HI (add rma (ext SI cdisp12))))))((mep (unit u-use-gpr (in usereg rma))(unit u-exec))))(dnci lbucpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))"lbucpa $crn,($rma+),$cdisp10"(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xC) (f-ext62 #x0) cdisp10)(sequence ()(c-call "check_option_cp" pc)(set crn (zext SI (mem QI rma)))(set rma (add rma cdisp10)))((mep (unit u-use-gpr (in usereg rma))(unit u-exec))))(dnci lhucpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5))"lhucpa $crn,($rma+),$cdisp10a2"(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xD) (f-ext62 #x0) cdisp10a2)(sequence ()(c-call "check_option_cp" pc)(set crn (zext SI (mem HI (and rma (inv SI 1)))))(set rma (add rma (ext SI cdisp10a2))))((mep (unit u-use-gpr (in usereg rma))(unit u-exec))))(dnci lbucpm0 "lbucpm0" (OPTIONAL_CP_INSN (MACH c5))"lbucpm0 $crn,($rma+),$cdisp10"(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x2) cdisp10)(sequence ()(c-call "check_option_cp" pc)(set crn (zext SI (mem QI rma)))(set rma (mod0 cdisp10)))((mep (unit u-use-gpr (in usereg rma))(unit u-exec))))(dnci lhucpm0 "lhucpm0" (OPTIONAL_CP_INSN (MACH c5))"lhucpm0 $crn,($rma+),$cdisp10a2"(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x2) cdisp10a2)(sequence ()(c-call "check_option_cp" pc)(set crn (zext SI (mem HI (and rma (inv SI 1)))))(set rma (mod0 cdisp10a2)))((mep (unit u-use-gpr (in usereg rma))(unit u-exec))))(dnci lbucpm1 "lbucpm1" (OPTIONAL_CP_INSN (MACH c5))"lbucpm1 $crn,($rma+),$cdisp10"(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x3) cdisp10)(sequence ()(c-call "check_option_cp" pc)(set crn (zext SI (mem QI rma)))(set rma (mod1 cdisp10)))((mep (unit u-use-gpr (in usereg rma))(unit u-exec))))(dnci lhucpm1 "lhucpm1" (OPTIONAL_CP_INSN (MACH c5))"lhucpm1 $crn,($rma+),$cdisp10a2"(+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x3) cdisp10a2)(sequence ()(c-call "check_option_cp" pc)(set crn (zext SI (mem HI (and rma (inv SI 1)))))(set rma (mod1 cdisp10a2)))((mep (unit u-use-gpr (in usereg rma))(unit u-exec))))(dnci uci "uci" ((MACH c5) VOLATILE)"uci $rn,$rm,$uimm16"(+ MAJ_15 rn rm (f-sub4 2) simm16)(set rn (c-call SI "do_UCI" rn rm (zext SI uimm16) pc))((mep (unit u-use-gpr (in usereg rm))(unit u-use-gpr (in usereg rn))(unit u-exec))))(dnf f-c5-rnm "register n/m" (all-mep-isas) 4 8)(dnf f-c5-rm "register m" (all-mep-isas) 8 4)(df f-c5-16u16 "general 16-bit u-val" (all-mep-isas) 16 16 UINT #f #f)(dnmf f-c5-rmuimm20 "20-bit immediate in Rm/Imm16" (all-mep-isas) UINT(f-c5-rm f-c5-16u16)(sequence () ; insert(set (ifield f-c5-rm) (srl (ifield f-c5-rmuimm20) 16))(set (ifield f-c5-16u16) (and (ifield f-c5-rmuimm20) #xffff)))(sequence () ; extract(set (ifield f-c5-rmuimm20) (or (ifield f-c5-16u16)(sll (ifield f-c5-rm) 16)))))(dnop c5rmuimm20 "20-bit immediate in rm and imm16" (all-mep-core-isas) h-uint f-c5-rmuimm20)(dnmf f-c5-rnmuimm24 "24-bit immediate in Rm/Imm16" (all-mep-isas) UINT(f-c5-rnm f-c5-16u16)(sequence () ; insert(set (ifield f-c5-rnm) (srl (ifield f-c5-rnmuimm24) 16))(set (ifield f-c5-16u16) (and (ifield f-c5-rnmuimm24) #xffff)))(sequence () ; extract(set (ifield f-c5-rnmuimm24) (or (ifield f-c5-16u16)(sll (ifield f-c5-rnm) 16)))))(dnop c5rnmuimm24 "24-bit immediate in rn, rm, and imm16" (all-mep-core-isas) h-uint f-c5-rnmuimm24)(dnci dsp "dsp" ((MACH c5) VOLATILE)"dsp $rn,$rm,$uimm16"(+ MAJ_15 rn rm (f-sub4 0) uimm16)(set rn (c-call SI "do_DSP" rn rm (zext SI uimm16) pc))((mep (unit u-use-gpr (in usereg rm))(unit u-use-gpr (in usereg rn))(unit u-exec))))(dnci dsp0 "dsp0" ((MACH c5) VOLATILE NO-DIS ALIAS)"dsp0 $c5rnmuimm24"(+ MAJ_15 c5rnmuimm24 (f-sub4 0))(c-call VOID "do_DSP" (zext SI c5rnmuimm24) pc)((mep (unit u-exec))))(dnci dsp1 "dsp1" ((MACH c5) VOLATILE NO-DIS ALIAS)"dsp1 $rn,$c5rmuimm20"(+ MAJ_15 rn (f-sub4 0) c5rmuimm20)(set rn (c-call SI "do_DSP" rn (zext SI c5rmuimm20) pc))((mep (unit u-use-gpr (in usereg rn))(unit u-exec))))

