URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [config/] [xtensa/] [xtensa.opt] - Rev 709
Compare with Previous | Blame | View Log
; Options for the Tensilica Xtensa port of the compiler.; Copyright (C) 2005, 2007, 2008, 2010 Free Software Foundation, Inc.;; This file is part of GCC.;; GCC is free software; you can redistribute it and/or modify it under; the terms of the GNU General Public License as published by the Free; Software Foundation; either version 3, or (at your option) any later; version.;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY; WARRANTY; without even the implied warranty of MERCHANTABILITY or; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License; for more details.;; You should have received a copy of the GNU General Public License; along with GCC; see the file COPYING3. If not see; <http://www.gnu.org/licenses/>.mconst16Target Report Mask(CONST16)Use CONST16 instruction to load constantsmforce-no-picTarget Report Mask(FORCE_NO_PIC)Disable position-independent code (PIC) for use in OS kernel codemlongcallsTargetUse indirect CALLXn instructions for large programsmtarget-alignTargetAutomatically align branch targets to reduce branch penaltiesmtext-section-literalsTargetIntersperse literal pools with code in the text sectionmserialize-volatileTarget Report Mask(SERIALIZE_VOLATILE)-mno-serialize-volatile Do not serialize volatile memory references with MEMW instructions
