OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [arm/] [neon/] [vclts16.c] - Rev 691

Compare with Previous | Blame | View Log

/* Test the `vclts16' ARM Neon intrinsic.  */
/* This file was autogenerated by neon-testgen.  */
 
/* { dg-do assemble } */
/* { dg-require-effective-target arm_neon_ok } */
/* { dg-options "-save-temps -O0" } */
/* { dg-add-options arm_neon } */
 
#include "arm_neon.h"
 
void test_vclts16 (void)
{
  uint16x4_t out_uint16x4_t;
  int16x4_t arg0_int16x4_t;
  int16x4_t arg1_int16x4_t;
 
  out_uint16x4_t = vclt_s16 (arg0_int16x4_t, arg1_int16x4_t);
}
 
/* { dg-final { scan-assembler "vcgt\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.