OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [arm/] [pr40956.c] - Rev 691

Compare with Previous | Blame | View Log

/* { dg-options "-Os -fpic" }  */
/* { dg-require-effective-target fpic } */
/* Make sure the constant "0" is loaded into register only once.  */
/* { dg-final { scan-assembler-times "mov\[\\t \]*r., #0" 1 } } */
 
int foo(int p, int* q)
{
  if (p!=9)
    *q = 0;
  else
    *(q+1) = 0;
  return 3;
}
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.