OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [cris/] [20011127-1.c] - Rev 801

Go to most recent revision | Compare with Previous | Blame | View Log

/* Copyright (C) 2001, 2007  Free Software Foundation.
   by Hans-Peter Nilsson  <hp@axis.com>
 
   Making sure that invalid asm operand modifiers don't cause an ICE.  */
 
/* { dg-do compile } */
/* { dg-options "-O2" } */
/* { dg-message "reg:SI|const_double:DF" "prune debug_rtx output" { target *-*-* } 0 } */
 
void
foo (void)
{
  /* The first case symbolizes the default case for CRIS.  */
  asm ("\n;# %w0" : : "r" (0));	/* { dg-error "modifier" } */
 
  /* These are explicit cases.  Luckily, a register is invalid in most of
     them.  */
  asm ("\n;# %b0" : : "r" (0));		/* { dg-error "modifier" } */
  asm ("\n;# %v0" : : "r" (0));		/* { dg-error "modifier" } */
  asm ("\n;# %P0" : : "r" (0));		/* { dg-error "modifier" } */
  asm ("\n;# %p0" : : "r" (0));		/* { dg-error "modifier" } */
  asm ("\n;# %z0" : : "r" (0));		/* { dg-error "modifier" } */
  asm ("\n;# %H0" : : "F" (0.5));	/* { dg-error "modifier" } */
  asm ("\n;# %e0" : : "r" (0));		/* { dg-error "modifier" } */
  asm ("\n;# %m0" : : "r" (0));		/* { dg-error "modifier" } */
  asm ("\n;# %A0" : : "r" (0));		/* { dg-error "modifier" } */
  asm ("\n;# %D0" : : "r" (0));		/* { dg-error "modifier" } */
  asm ("\n;# %T0" : : "r" (0));		/* { dg-error "modifier" } */
  /* Add more must-not-ICE asm errors here as we find them ICEing.  */
}
 

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.