OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [i386/] [bmi-1.c] - Rev 691

Compare with Previous | Blame | View Log

/* { dg-do compile } */
/* { dg-options "-O2 -mbmi " } */
/* { dg-final { scan-assembler "andn\[^\\n]*(%|)eax" } } */
/* { dg-final { scan-assembler "bextr\[^\\n]*(%|)eax" } } */
/* { dg-final { scan-assembler "blsi\[^\\n]*(%|)eax" } } */
/* { dg-final { scan-assembler "blsmsk\[^\\n]*(%|)eax" } } */
/* { dg-final { scan-assembler "blsr\[^\\n]*(%|)eax" } } */
/* { dg-final { scan-assembler "tzcntl\[^\\n]*(%|)eax" } } */
 
#include <x86intrin.h>
 
unsigned int
func_andn32 (unsigned int X, unsigned int Y)
{
  return __andn_u32(X, Y);
}
 
unsigned int
func_bextr32 (unsigned int X, unsigned int Y)
{
  return __bextr_u32(X, Y);
}
 
unsigned int
func_blsi32 (unsigned int X)
{
  return __blsi_u32(X);
}
 
unsigned int
func_blsmsk32 (unsigned int X)
{
  return __blsmsk_u32(X);
}
 
unsigned int
func_blsr32 (unsigned int X)
{
  return __blsr_u32(X);
}
 
unsigned int
func_tzcnt32 (unsigned int X)
{
  return __tzcnt_u32(X);
}
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.