URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [gnu-dev/] [or1k-gcc/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [altivec-cell-6.c] - Rev 801
Go to most recent revision | Compare with Previous | Blame | View Log
/* { dg-do compile } */ /* { dg-require-effective-target powerpc_altivec_ok } */ /* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */ #include <altivec.h> /* This used to ICE with reloading of a constant address. */ vector float f(void) { vector float * a = (void*)16; return vec_lvlx (0, a); }
Go to most recent revision | Compare with Previous | Blame | View Log