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https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [arm/] [neon-cond-bad.l] - Rev 816
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[^:]*: Assembler messages:[^:]*:10: Error: instruction cannot be conditional -- `vmoveq q0,q1'[^:]*:11: Error: instruction cannot be conditional -- `vmoveq d0,d1'[^:]*:12: Error: instruction cannot be conditional -- `vmoveq\.i32 q0,#0'[^:]*:13: Error: instruction cannot be conditional -- `vmoveq\.i32 d0,#0'[^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 d0,d1,d2'[^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 q0,q1,q2'[^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 d0,d1,d2'[^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 q0,q1,q2'[^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 d0,d1,d2'[^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 q0,q1,q2'[^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 d0,d1,d2'[^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 q0,q1,q2'[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 d0,d1,d2'[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 q0,q1,q2'[^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 d0,d1'[^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 q0,q1'[^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 d0,d1'[^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 q0,q1'[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 d0,d1'[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 q0,q1'[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 d0,d1'[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 q0,q1'[^:]*:50: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 d0,d1'[^:]*:50: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 q0,q1'[^:]*:51: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 d0,d1'[^:]*:51: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 q0,q1'[^:]*:56: Error: instruction cannot be conditional -- `vdupeq\.32 d0,d1\[0\]'[^:]*:57: Error: instruction cannot be conditional -- `vdupeq\.32 q0,d1\[1\]'