OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [d30v/] [guard-debug.s] - Rev 816

Compare with Previous | Blame | View Log

# Same as guard.s but here we are testing debug (-g) assembly
# On the D30V, assembling with -g should disable the VLIW packing
# and put only one instruction per line.	
 
	.text
 
	add	r1,r2,r3
	add/al	r1,r2,r3
	add/tx	r1,r2,r3
	add/fx	r1,r2,r3
	add/xt	r1,r2,r3
	add/xf	r1,r2,r3
	add/tt	r1,r2,r3
	add/tf	r1,r2,r3
 
 
 
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.