OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [elf/] [elf.exp] - Rev 830

Go to most recent revision | Compare with Previous | Blame | View Log

#
# elf tests
#

proc run_elf_list_test { name suffix opts readelf_opts readelf_pipe } {
    global READELF
    global srcdir subdir
    set testname "elf $name list"
    set file $srcdir/$subdir/$name
    gas_run ${name}.s "$opts -o dump.o" ">&dump.out"
    if { ![string match "" $opts]
          && [regexp_diff "dump.out" "${file}.l"] } then {
        fail $testname
        verbose "output is [file_contents "dump.out"]" 2
        return
    }
    send_log "$READELF $readelf_opts dump.o $readelf_pipe > dump.out\n"
    set status [gas_host_run "$READELF $readelf_opts dump.o" ">readelf.out"]
    if { [lindex $status 0] != 0 || ![string match "" [lindex $status 1]] } then {
        send_log "[lindex $status 1]\n"
        fail $testname
        return
    }
    catch "exec cat readelf.out $readelf_pipe > dump.out\n" comp_output
    if ![string match "" $comp_output] then {
        send_log "$comp_output\n"
        fail $testname
        return
    }
    verbose_eval {[file_contents "dump.out"]} 3
    if { [regexp_diff "dump.out" "${file}.e${suffix}"] } then {
        fail $testname
        verbose "output is [file_contents "dump.out"]" 2
        return
    }
    pass $testname
}

# We're testing bits in obj-elf -- don't run on anything else.
if { ([istarget "*-*-*elf*"]            
      || [istarget "*-*-linux*"]
      || [istarget "m6811-*"]
      || [istarget "m6812-*"]
      || [istarget "sparc*-*-solaris*"]
      || [istarget "mips*-*-irix6*"]
      || [istarget "arm*-*-eabi"])
     && ![istarget *-*-linux*aout*]
     && ![istarget *-*-linux*coff*]
     && ![istarget *-*-linux*oldld*]
     && ![istarget sh64*-*-linux*]
} then {
    set target_machine ""
    if {[istarget "mips*-*-*"]} then {
        set target_machine -mips
    }
    if {[istarget m32r*-*-*]} then {
        set target_machine -m32r
    }
    if {[istarget "score-*-*"]} then {
        set target_machine -score
    }
    if {[istarget "xtensa*-*-*"]} then {
        set target_machine -xtensa
    }
    if { ([istarget "*arm*-*-*"]
          || [istarget "xscale*-*-*"]) } {
        
        if { ([istarget "*-*-*eabi"]
              || [istarget "*-*-linux-*"]
              || [istarget "*-*-symbianelf"])} then {
            set target_machine -armeabi
        } else {
            set target_machine -armelf
        }
    }

    # The MN10300 and Xtensa ports disable the assembler's call frame
    # optimization because it interfers with link-time relaxation of
    # function prologues.
    if {![istarget "mn10300-*-*"]
        && ![istarget "xtensa*-*-*"]
        && ![istarget "am3*-*-*"]} then {    
      run_dump_test "ehopt0"
    }
    run_dump_test "group0a" 
    run_dump_test "group0b" 
    run_dump_test "group1a" 
    run_dump_test "group1b" 
    case $target_triplet in {
        { alpha*-*-* } { }
        { hppa*-*-* } { }
        { iq2000*-*-* } { }
        { mips*-*-* } { }
        { *c54x*-*-* } { }
        default {
            # The next test can fail if the target does not convert fixups
            # against ordinary symbols into relocations against section symbols.
            # This is usually revealed by the error message:
            #  symbol `sym' required but not present
            setup_xfail "cr16-*-*" "h8300-*-*" "mn10300-*-*"
            run_dump_test redef
            run_dump_test equ-reloc
        }
    }
    run_dump_test "section0" 
    run_dump_test "section1" 
    run_elf_list_test "section2" "$target_machine" "-al" "-s" ""
    run_dump_test "section3" 
    run_dump_test "section4"
    run_elf_list_test "section5" "" "-al" "-SW" "| grep \" \\\\.test\\\[0-9\\\]\""
    run_dump_test "struct" 
    run_dump_test "symver" 
    run_elf_list_test "type" "" "" "-s" "| grep \"1 \\\[FONTC\\\]\""
    run_dump_test "section6" 
    run_dump_test "section7" 
}

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.