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https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [gnu-old/] [binutils-2.18.50/] [gas/] [testsuite/] [gas/] [ia64/] [opc-a-err.l] - Rev 856
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.*: Assembler messages:
.*:1: Error: Operand 2 of `adds' should be a 14-bit .*
.*:2: Error: Operand 2 of `adds' should be a 14-bit .*
.*:4: Error: Operand 2 of `addl' should be a 22-bit .*
.*:5: Error: Operand 2 of `addl' should be a 22-bit .*
.*:6: Error: Operand 3 of `addl' should be a general register r0-r3
.*:8: Error: Operand 2 of `sub' should be .*
.*:9: Error: Operand 2 of `sub' should be .*
.*:11: Error: Operand 2 of `and' should be .*
.*:12: Error: Operand 2 of `and' should be .*
.*:14: Error: Operand 2 of `or' should be .*
.*:15: Error: Operand 2 of `or' should be .*
.*:17: Error: Operand 2 of `xor' should be .*
.*:18: Error: Operand 2 of `xor' should be .*
.*:20: Error: Operand 2 of `andcm' should be .*
.*:21: Error: Operand 2 of `andcm' should be .*
.*:23: Error: Operand [34] of `cmp4.lt.or' should be r0
.*:24: Error: Operand [34] of `cmp4.lt.or' should be r0
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