OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gcc-4.2.2/] [gcc/] [testsuite/] [gcc.target/] [i386/] [pr27696.c] - Rev 154

Go to most recent revision | Compare with Previous | Blame | View Log

/* PR target/27696
   The testcase below uses to trigger an ICE.  */
 
/* { dg-do compile } */
/* { dg-options "-msse3" } */
 
void
foo (void const * P, unsigned int E, unsigned int H)
{
  __builtin_ia32_monitor (P, E, H);
}
 

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.