OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [common/] [tconfig.in] - Rev 816

Go to most recent revision | Compare with Previous | Blame | View Log

/* Default target configuration file.
   To override this, create file `tconfig.in' in the simulator's
   source directory.  */

/* Define this if the simulator supports profiling.
   See the mips simulator for an example.
   This enables the `-p foo' and `-s bar' options.
   The target is required to provide sim_set_profile{,_size}.  */
/* #define SIM_HAVE_PROFILE */

/* Define this if the simulator uses an instruction cache.
   See the h8/300 simulator for an example.
   This enables the `-c size' option to set the size of the cache.
   The target is required to provide sim_set_simcache_size.  */
/* #define SIM_HAVE_SIMCACHE */

/* Define this if the target cpu is bi-endian
   and the simulator supports it.  */
/* #define SIM_HAVE_BIENDIAN */

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.