OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [d10v-elf/] [t-ae-st2w-ip.s] - Rev 840

Compare with Previous | Blame | View Log

.include "t-macros.i"
 
	start
 
	PSW_BITS = 0
	point_dmap_at_imem
	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w
 
	ldi r10, #0x4000
	st2w r8, @r10+
 
	ldi r10, #0x4001
test_st2w:
	st2w r8,@r10+
	nop
	exit47
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.