OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [d10v-elf/] [t-rdt.s] - Rev 840

Compare with Previous | Blame | View Log

.include "t-macros.i"
 
	start
 
	PSW_BITS = PSW_C|PSW_F0|PSW_F1
 
	ldi	r6, #success@word
	mvtc	r6, dpc
	ldi	r6, #PSW_BITS
	mvtc	r6, dpsw
 
test_rdt:
	RTD
	exit47
 
success:
	checkpsw2 1 PSW_BITS
	exit0
 

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.