OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [adc.cgs] - Rev 24

Go to most recent revision | Compare with Previous | Blame | View Log

# arm testcase for adc
# mach: all

# ??? Unfinished, more tests needed.

        .include "testutils.inc"

        start

# adc$cond${set-cc?} $rd,$rn,$imm12

        .global adc_imm
adc_imm:
        mvi_h_gr r4,1
        mvi_h_cnvz 0,0,0,0
        adc r5,r4,#1
        test_h_cnvz 0,0,0,0
        test_h_gr r5,2

# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftimm}

        .global adc_reg_imm_shift
adc_reg_imm_shift:
        mvi_h_gr r4,1
        mvi_h_gr r5,1
        mvi_h_cnvz 0,0,0,0
        adc r6,r4,r5,lsl #2
        test_h_cnvz 0,0,0,0
        test_h_gr r6,5

# adc$cond${set-cc?} $rd,$rn,$rm,${operand2-shifttype} ${operand2-shiftreg}

        .global adc_reg_reg_shift
adc_reg_reg_shift:
        mvi_h_gr r4,1
        mvi_h_gr r5,1
        mvi_h_gr r6,2
        mvi_h_cnvz 0,0,0,0
        adc r7,r4,r5,lsl r6
        test_h_cnvz 0,0,0,0
        test_h_gr r7,5

        pass

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.