OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [b.cgs] - Rev 24

Go to most recent revision | Compare with Previous | Blame | View Log

# arm testcase for b$cond $offset24
# mach: all

# ??? Still need to test edge cases.

        .include "testutils.inc"

        start

        .global b
b:

# b foo

        b balways1
        fail
balways1:

# beq foo

        mvi_h_gr r4,4
        mvi_h_gr r5,4
        cmp r4,r5
        beq beq1
        fail
beq1:
        mvi_h_gr r5,5
        cmp r4,r5
        beq beq2
        b beq3
beq2:
        fail
beq3:

# bne foo

        mvi_h_gr r4,4
        mvi_h_gr r5,5
        cmp r4,r5
        bne bne1
        fail
bne1:
        mvi_h_gr r5,4
        cmp r4,r5
        bne bne2
        b bne3
bne2:
        fail
bne3:

# bcs foo

        mvi_h_cnvz 1,0,0,0
        bcs bcs1
        fail
bcs1:
        mvi_h_cnvz 0,0,0,0
        bcs bcs2
        b bcs3
bcs2:
        fail
bcs3:

# bcc foo

        mvi_h_cnvz 0,0,0,0
        bcc bcc1
        fail
bcc1:
        mvi_h_cnvz 1,0,0,0
        bcc bcc2
        b bcc3
bcc2:
        fail
bcc3:

# bmi foo

        mvi_h_cnvz 0,1,0,0
        bmi bmi1
        fail
bmi1:
        mvi_h_cnvz 0,0,0,0
        bmi bmi2
        b bmi3
bmi2:
        fail
bmi3:

# bpl foo

        mvi_h_cnvz 0,0,0,0
        bpl bpl1
        fail
bpl1:
        mvi_h_cnvz 0,1,0,0
        bpl bpl2
        b bpl3
bpl2:
        fail
bpl3:

# bvs foo

        mvi_h_cnvz 0,0,1,0
        bvs bvs1
        fail
bvs1:
        mvi_h_cnvz 0,0,0,0
        bvs bvs2
        b bvs3
bvs2:
        fail
bvs3:

# bvc foo

        mvi_h_cnvz 0,0,0,0
        bvc bvc1
        fail
bvc1:
        mvi_h_cnvz 0,0,1,0
        bvc bvc2
        b bvc3
bvc2:
        fail
bvc3:

# bhi foo

        mvi_h_gr r4,5
        mvi_h_gr r5,4
        cmp r4,r5
        bhi bhi1
        fail
bhi1:
        mvi_h_gr r5,5
        cmp r4,r5
        bhi bhi2
        b bhi3
bhi2:
        fail
bhi3:
        mvi_h_gr r5,6
        cmp r4,r5
        bhi bhi4
        b bhi5
bhi4:
        fail
bhi5:

# bls foo

        mvi_h_gr r4,4
        mvi_h_gr r5,5
        cmp r4,r5
        bls bls1
        fail
bls1:
        mvi_h_gr r5,4
        cmp r4,r5
        bls bls2
        fail
bls2:
        mvi_h_gr r5,3
        cmp r4,r5
        bls bls3
        b bls4
bls3:
        fail
bls4:

# bge foo

        mvi_h_gr r4,4
        mvi_h_gr r5,4
        cmp r4,r5
        bge bge1
        fail
bge1:
        mvi_h_gr r5,3
        cmp r4,r5
        bge bge2
        fail
bge2:
        mvi_h_gr r5,5
        cmp r4,r5
        bge bge3
        b bge4
bge3:
        fail
bge4:

# blt foo

        mvi_h_gr r4,4
        mvi_h_gr r5,5
        cmp r4,r5
        blt blt1
        fail
blt1:
        mvi_h_gr r5,4
        cmp r4,r5
        blt blt2
        b blt3
blt2:
        fail
blt3:
        mvi_h_gr r5,3
        cmp r4,r5
        blt blt4
        b blt5
blt4:
        fail
blt5:

# bgt foo

        mvi_h_gr r4,4
        mvi_h_gr r5,3
        cmp r4,r5
        bgt bgt1
        fail
bgt1:
        mvi_h_gr r5,4
        cmp r4,r5
        bgt bgt2
        b bgt3
bgt2:
        fail
bgt3:
        mvi_h_gr r5,5
        cmp r4,r5
        bgt bgt4
        b bgt5
bgt4:
        fail
bgt5:

# ble foo

        mvi_h_gr r4,4
        mvi_h_gr r5,4
        cmp r4,r5
        ble ble1
        fail
ble1:
        mvi_h_gr r5,5
        cmp r4,r5
        ble ble2
        fail
ble2:
        mvi_h_gr r5,3
        cmp r4,r5
        ble ble3
        b ble4
ble3:
        fail
ble4:

        pass

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.