URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wpack.cgs] - Rev 827
Go to most recent revision | Compare with Previous | Blame | View Log
# Intel(r) Wireless MMX(tm) technology testcase for WPACK# mach: xscale# as: -mcpu=xscale+iwmmxt.include "testutils.inc"start.global wpackwpack:# Enable access to CoProcessors 0 & 1 before# we attempt these instructions.mvi_h_gr r1, 3mcr p15, 0, r1, cr15, cr1, 0# Test Halfword, Unsigned Saturation, Packingmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x00000000mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wpackhus wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111111test_h_gr r3, 0x00000000test_h_gr r4, 0x0000fffftest_h_gr r5, 0x0000ffff# Test Halfword, Signed Saturation, Packingmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x00000000mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wpackhss wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111111test_h_gr r3, 0x00000000test_h_gr r4, 0x80807f7ftest_h_gr r5, 0x00007f7f# Test Word, Unsigned Saturation, Packingmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x00000000mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wpackwus wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111111test_h_gr r3, 0x00000000test_h_gr r4, 0x0000fffftest_h_gr r5, 0x0000ffff# Test Word, Signed Saturation, Packingmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x00000000mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wpackwss wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111111test_h_gr r3, 0x00000000test_h_gr r4, 0x80007ffftest_h_gr r5, 0x00007fff# Test Double Word, Unsigned Saturation, Packingmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x00000000mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wpackdus wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111111test_h_gr r3, 0x00000000test_h_gr r4, 0x00000000test_h_gr r5, 0x11111111# Test Double Word, Signed Saturation, Packingmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x00000000mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wpackdss wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111111test_h_gr r3, 0x00000000test_h_gr r4, 0x80000000test_h_gr r5, 0x11111111pass
Go to most recent revision | Compare with Previous | Blame | View Log