OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wshufh.cgs] - Rev 840

Compare with Previous | Blame | View Log

# Intel(r) Wireless MMX(tm) technology testcase for WSHUFH
# mach: xscale
# as: -mcpu=xscale+iwmmxt

        .include "testutils.inc"

        start

        .global wshufh
wshufh:
        # Enable access to CoProcessors 0 & 1 before
        # we attempt these instructions.

        mvi_h_gr   r1, 3
        mcr        p15, 0, r1, cr15, cr1, 0
        
        mvi_h_gr   r0, 0x12345678
        mvi_h_gr   r1, 0x9abcdef0
        mvi_h_gr   r2, 0
        mvi_h_gr   r3, 0

        tmcrr      wr0, r0, r1
        tmcrr      wr1, r2, r3

        wshufh     wr1, wr0, #0x1b
        
        tmrrc      r0, r1, wr0
        tmrrc      r2, r3, wr1
        
        test_h_gr  r0, 0x12345678
        test_h_gr  r1, 0x9abcdef0
        test_h_gr  r2, 0xdef09abc
        test_h_gr  r3, 0x56781234
        
        pass

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.