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[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wsll.cgs] - Rev 24
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# Intel(r) Wireless MMX(tm) technology testcase for WSLL# mach: xscale# as: -mcpu=xscale+iwmmxt.include "testutils.inc"start.global wsllwsll:# Enable access to CoProcessors 0 & 1 before# we attempt these instructions.mvi_h_gr r1, 3mcr p15, 0, r1, cr15, cr1, 0# Test Halfword Logical Shift Leftmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111104mvi_h_gr r3, 0x11111111mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wsllh wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111104test_h_gr r3, 0x11111111test_h_gr r4, 0x23406780test_h_gr r5, 0xabc0ef00# Test Halfword Aritc Shift Left by CG registermvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111104mvi_h_gr r3, 0mvi_h_gr r4, 0tmcrr wr0, r0, r1tmcr wcgr1, r2tmcrr wr1, r3, r4wsllhg wr1, wr0, wcgr1tmrrc r0, r1, wr0tmrc r2, wcgr1tmrrc r3, r4, wr1test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111104test_h_gr r3, 0x23406780test_h_gr r4, 0xabc0ef00# Test Word Logical Shift Leftmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111104mvi_h_gr r3, 0x11111111mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wsllw wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111104test_h_gr r3, 0x11111111test_h_gr r4, 0x23456780test_h_gr r5, 0xabcdef00# Test Word Logical Shift Left by CG registermvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111104mvi_h_gr r3, 0mvi_h_gr r4, 0tmcrr wr0, r0, r1tmcr wcgr2, r2tmcrr wr1, r3, r4wsllwg wr1, wr0, wcgr2tmrrc r0, r1, wr0tmrc r2, wcgr2tmrrc r3, r4, wr1test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111104test_h_gr r3, 0x23456780test_h_gr r4, 0xabcdef00# Test Double Word Logical Shift Leftmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdefcmvi_h_gr r2, 0x11111104mvi_h_gr r3, 0x11111111mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wslld wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdefctest_h_gr r2, 0x11111104test_h_gr r3, 0x11111111test_h_gr r4, 0x23456780test_h_gr r5, 0xabcdefc1# Test Double Word Logical Shift Left by CG registermvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdefcmvi_h_gr r2, 0x11111104mvi_h_gr r3, 0mvi_h_gr r4, 0tmcrr wr0, r0, r1tmcr wcgr3, r2tmcrr wr1, r3, r4wslldg wr1, wr0, wcgr3tmrrc r0, r1, wr0tmrc r2, wcgr3tmrrc r3, r4, wr1test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdefctest_h_gr r2, 0x11111104test_h_gr r3, 0x23456780test_h_gr r4, 0xabcdefc1pass
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