URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wsra.cgs] - Rev 157
Go to most recent revision | Compare with Previous | Blame | View Log
# Intel(r) Wireless MMX(tm) technology testcase for WSRA# mach: xscale# as: -mcpu=xscale+iwmmxt.include "testutils.inc"start.global wsrawsra:# Enable access to CoProcessors 0 & 1 before# we attempt these instructions.mvi_h_gr r1, 3mcr p15, 0, r1, cr15, cr1, 0# Test Halfword Arithmetic Shift Rightmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111104mvi_h_gr r3, 0x11111111mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wsrah wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111104test_h_gr r3, 0x11111111test_h_gr r4, 0x01230567test_h_gr r5, 0xf9abfdef# Test Halfword Arithmetic Shift Right by CG registermvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111104mvi_h_gr r3, 0mvi_h_gr r4, 0tmcrr wr0, r0, r1tmcr wcgr1, r2tmcrr wr1, r3, r4wsrahg wr1, wr0, wcgr1tmrrc r0, r1, wr0tmrc r2, wcgr1tmrrc r3, r4, wr1test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111104test_h_gr r3, 0x01230567test_h_gr r4, 0xf9abfdef# Test Word Arithmetic Shift Rightmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111104mvi_h_gr r3, 0x11111111mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wsraw wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111104test_h_gr r3, 0x11111111test_h_gr r4, 0x01234567test_h_gr r5, 0xf9abcdef# Test Word Arithmetic Shift Right by CG registermvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdef0mvi_h_gr r2, 0x11111104mvi_h_gr r3, 0mvi_h_gr r4, 0tmcrr wr0, r0, r1tmcr wcgr2, r2tmcrr wr1, r3, r4wsrawg wr1, wr0, wcgr2tmrrc r0, r1, wr0tmrc r2, wcgr2tmrrc r3, r4, wr1test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdef0test_h_gr r2, 0x11111104test_h_gr r3, 0x01234567test_h_gr r4, 0xf9abcdef# Test Double Word Arithmetic Shift Rightmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdefcmvi_h_gr r2, 0x11111104mvi_h_gr r3, 0x11111111mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wsrad wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdefctest_h_gr r2, 0x11111104test_h_gr r3, 0x11111111test_h_gr r4, 0xc1234567test_h_gr r5, 0xf9abcdef# Test Double Word Arithmetic Shift Right by CG registermvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcdefcmvi_h_gr r2, 0x11111104mvi_h_gr r3, 0mvi_h_gr r4, 0tmcrr wr0, r0, r1tmcr wcgr3, r2tmcrr wr1, r3, r4wsradg wr1, wr0, wcgr3tmrrc r0, r1, wr0tmrc r2, wcgr3tmrrc r3, r4, wr1test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcdefctest_h_gr r2, 0x11111104test_h_gr r3, 0xc1234567test_h_gr r4, 0xf9abcdefpass
Go to most recent revision | Compare with Previous | Blame | View Log