URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [arm/] [iwmmxt/] [wsub.cgs] - Rev 816
Go to most recent revision | Compare with Previous | Blame | View Log
# Intel(r) Wireless MMX(tm) technology testcase for WSUB# mach: xscale# as: -mcpu=xscale+iwmmxt.include "testutils.inc"start.global wsubwsub:# Enable access to CoProcessors 0 & 1 before# we attempt these instructions.mvi_h_gr r1, 3mcr p15, 0, r1, cr15, cr1, 0# Test Unsaturated Byte subtractionmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcde00mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x11111111mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wsubb wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcde00test_h_gr r2, 0x11111111test_h_gr r3, 0x11111111test_h_gr r4, 0x01234567test_h_gr r5, 0x89abcdef# Test Unsigned saturated Byte subtractionmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcde00mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x11111111mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wsubbus wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcde00test_h_gr r2, 0x11111111test_h_gr r3, 0x11111111test_h_gr r4, 0x01234567test_h_gr r5, 0x89abcd00# Test Signed saturated Byte subtractionmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcde00mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x11111111mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wsubbss wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcde00test_h_gr r2, 0x11111111test_h_gr r3, 0x11111111test_h_gr r4, 0x01234567test_h_gr r5, 0x89abcdef# Test Unsaturated Halfword subtractionmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcde00mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x11111111mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wsubh wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcde00test_h_gr r2, 0x11111111test_h_gr r3, 0x11111111test_h_gr r4, 0x01234567test_h_gr r5, 0x89abccef# Test Unsigned saturated Halfword subtractionmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcde00mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x11111111mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wsubhus wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcde00test_h_gr r2, 0x11111111test_h_gr r3, 0x11111111test_h_gr r4, 0x01234567test_h_gr r5, 0x89abccef# Test Signed saturated Halfword subtractionmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcde00mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x11111111mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wsubhss wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcde00test_h_gr r2, 0x11111111test_h_gr r3, 0x11111111test_h_gr r4, 0x01234567test_h_gr r5, 0x89abccef# Test Unsaturated Word subtractionmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcde00mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x11111111mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wsubw wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcde00test_h_gr r2, 0x11111111test_h_gr r3, 0x11111111test_h_gr r4, 0x01234567test_h_gr r5, 0x89abccef# Test Unsigned saturated Word subtractionmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcde00mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x11111111mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wsubwus wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcde00test_h_gr r2, 0x11111111test_h_gr r3, 0x11111111test_h_gr r4, 0x01234567test_h_gr r5, 0x89abccef# Test Signed saturated Word subtractionmvi_h_gr r0, 0x12345678mvi_h_gr r1, 0x9abcde00mvi_h_gr r2, 0x11111111mvi_h_gr r3, 0x11111111mvi_h_gr r4, 0mvi_h_gr r5, 0tmcrr wr0, r0, r1tmcrr wr1, r2, r3tmcrr wr2, r4, r5wsubwss wr2, wr0, wr1tmrrc r0, r1, wr0tmrrc r2, r3, wr1tmrrc r4, r5, wr2test_h_gr r0, 0x12345678test_h_gr r1, 0x9abcde00test_h_gr r2, 0x11111111test_h_gr r3, 0x11111111test_h_gr r4, 0x01234567test_h_gr r5, 0x89abccefpass
Go to most recent revision | Compare with Previous | Blame | View Log