OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [fr30/] [addn.cgs] - Rev 816

Go to most recent revision | Compare with Previous | Blame | View Log

# fr30 testcase for addn $Rj,$Ri, addn $u4,$Rj
# mach(): fr30

        .include "testutils.inc"

        START

        .text
        .global addn
addn:
        ; Test addn $Rj,$Ri
        mvi_h_gr        1,r7
        mvi_h_gr        2,r8
        set_cc          0x0f            ; Set mask opposite of normal result
        addn            r7,r8
        test_cc         1 1 1 1
        test_h_gr       3,r8

        mvi_h_gr        0x7fffffff,r7
        mvi_h_gr        1,r8
        set_cc          0x05            ; Set mask opposite of normal result
        addn            r7,r8
        test_cc         0 1 0 1
        test_h_gr       0x80000000,r8

        set_cc          0x08            ; Set mask opposite of normal result
        addn            r8,r8
        test_cc         1 0 0 0
        test_h_gr       0,r8

        ; Test addn $u4Ri
        mvi_h_gr        4,r8
        set_cc          0x0f            ; Set mask opposite of normal result
        addn            0,r8
        test_cc         1 1 1 1
        test_h_gr       4,r8
        set_cc          0x0f            ; Set mask opposite of normal result
        addn            1,r8
        test_cc         1 1 1 1
        test_h_gr       5,r8
        set_cc          0x0f            ; Set mask opposite of normal result
        addn            15,r8
        test_cc         1 1 1 1
        test_h_gr       20,r8
        mvi_h_gr        0x7fffffff,r8   ; test neg and overflow bits
        set_cc          0x05            ; Set mask opposite of normal result
        addn            1,r8
        test_cc         0 1 0 1
        test_h_gr       0x80000000,r8
        set_cc          0x08            ; Set mask opposite of normal result
        addn            r8,r8           ; test zero, carry and overflow bits
        test_cc         1 0 0 0;
        test_h_gr       0,r8

        pass

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.