URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [fr30/] [dmov.cgs] - Rev 816
Go to most recent revision | Compare with Previous | Blame | View Log
# fr30 testcase for dmov
# mach(): fr30
.include "testutils.inc"
START
.text
.global dmov
dmov:
; Test dmov @$dir10,$R13
mvi_h_gr 0xdeadbeef,r1
mvi_h_gr 0x200,r2
mvr_h_mem r1,r2
set_cc 0x0f ; Condition codes shouldn't change
dmov @0x200,r13
test_cc 1 1 1 1
test_h_gr 0xdeadbeef,r13
; Test dmov $R13,@$dir10
mvi_h_gr 0xbeefdead,r13
set_cc 0x0e ; Condition codes shouldn't change
dmov r13,@0x200
test_cc 1 1 1 0
test_h_mem 0xbeefdead,r2
; Test dmov @$dir10,@R13+
mvi_h_gr 0x1fc,r13
set_cc 0x0d ; Condition codes shouldn't change
dmov @0x200,@r13+
test_cc 1 1 0 1
mvi_h_gr 0x1fc,r2
test_h_mem 0xbeefdead,r2
inci_h_gr 4,r2
test_h_mem 0xbeefdead,r2
test_h_gr 0x200,r13
; Test dmov @$R13+,@$dir10
mvi_h_gr 0x1fc,r13
mvi_h_mem 0xdeadbeef,r13
set_cc 0x0c ; Condition codes shouldn't change
dmov @r13+,@0x200
test_cc 1 1 0 0
mvi_h_gr 0x1fc,r2
test_h_mem 0xdeadbeef,r2
inci_h_gr 4,r2
test_h_mem 0xdeadbeef,r2
test_h_gr 0x200,r13
; Test dmov @$dir10,@-R15
mvi_h_gr 0x200,r15
mvi_h_mem 0xdeadbeef,r15
set_cc 0x0b ; Condition codes shouldn't change
dmov @0x200,@-r15
test_cc 1 0 1 1
mvi_h_gr 0x1fc,r2
test_h_mem 0xdeadbeef,r2
inci_h_gr 4,r2
test_h_mem 0xdeadbeef,r2
test_h_gr 0x1fc,r15
; Test dmov @$R15+,@$dir10
mvi_h_gr 0x1fc,r15
mvi_h_mem 0xbeefdead,r15
set_cc 0x0a ; Condition codes shouldn't change
dmov @r15+,@0x200
test_cc 1 0 1 0
mvi_h_gr 0x1fc,r2
test_h_mem 0xbeefdead,r2
inci_h_gr 4,r2
test_h_mem 0xbeefdead,r2
test_h_gr 0x200,r15
pass
Go to most recent revision | Compare with Previous | Blame | View Log