OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [fr30/] [lduh.cgs] - Rev 157

Go to most recent revision | Compare with Previous | Blame | View Log

# fr30 testcase for
# mach(): fr30
# lduh $Rj,$Ri
# lduh @($R13,$Rj),$Ri
# lduh @($R14,$disp9),$Ri

        .include "testutils.inc"

        START

        .text
        .global lduh
lduh:
        ; Test lduh $Rj,$Ri
        mvi_h_mem       #0x0000beef,sp
        set_cc          0x0f            ; condition codes should not change
        lduh            @sp,r7
        test_cc         1 1 1 1
        test_h_gr       0,r7

        mvi_h_mem       #0x0001beef,sp
        set_cc          0x07            ; condition codes should not change
        lduh            @sp,r7
        test_cc         0 1 1 1
        test_h_gr       1,r7

        mvi_h_mem       #0x7fffbeef,sp
        set_cc          0x0b            ; condition codes should not change
        lduh            @sp,r7
        test_cc         1 0 1 1
        test_h_gr       0x7fff,r7

        mvi_h_mem       #0x8000beef,sp
        set_cc          0x0d            ; condition codes should not change
        lduh            @sp,r7
        test_cc         1 1 0 1
        test_h_gr       0x8000,r7

        mvi_h_mem       #0xffffbeef,sp
        set_cc          0x0e            ; condition codes should not change
        lduh            @sp,r7
        test_cc         1 1 1 0
        test_h_gr       0xffff,r7

        ; Test lduh @($R13,$Rj),$Ri
        mvr_h_gr        sp,r13
        inci_h_gr       -8,r13
        mvi_h_gr        8,r8

        mvi_h_mem       #0x0000beef,sp
        set_cc          0x0f            ; condition codes should not change
        lduh            @(r13,r8),r7
        test_cc         1 1 1 1
        test_h_gr       0,r7

        mvi_h_mem       #0x0001beef,sp
        set_cc          0x07            ; condition codes should not change
        lduh            @(r13,r8),r7
        test_cc         0 1 1 1
        test_h_gr       1,r7

        mvi_h_mem       #0x7fffbeef,sp
        set_cc          0x0b            ; condition codes should not change
        lduh            @(r13,r8),r7
        test_cc         1 0 1 1
        test_h_gr       0x7fff,r7

        mvi_h_mem       #0x8000beef,sp
        set_cc          0x0d            ; condition codes should not change
        lduh            @(r13,r8),r7
        test_cc         1 1 0 1
        test_h_gr       0x8000,r7

        mvi_h_mem       #0xffffbeef,sp
        set_cc          0x0e            ; condition codes should not change
        lduh            @(r13,r8),r7
        test_cc         1 1 1 0
        test_h_gr       0xffff,r7

        ; Test lduh @($R14,$disp9),$Ri
        mvi_h_mem       #0xdeadbeef,sp
        mvr_h_gr        sp,r14
        mvi_h_gr        -0xfe,r8
        add_h_gr        r8,r14

        set_cc          0x0f            ; condition codes should not change
        lduh            @(r14,0xfe),r7
        test_cc         1 1 1 1
        test_h_gr       0xdead,r7

        inci_h_gr       0x7e,r14
        set_cc          0x07            ; condition codes should not change
        lduh            @(r14,0x80),r7
        test_cc         0 1 1 1
        test_h_gr       0xdead,r7

        inci_h_gr       0x80,r14
        set_cc          0x0b            ; condition codes should not change
        lduh            @(r14,0x0),r7
        test_cc         1 0 1 1
        test_h_gr       0xdead,r7

        inci_h_gr       0x80,r14
        set_cc          0x0d            ; condition codes should not change
        lduh            @(r14,-0x80),r7
        test_cc         1 1 0 1
        test_h_gr       0xdead,r7

        inci_h_gr       0x80,r14
        set_cc          0x0e            ; condition codes should not change
        lduh            @(r14,-0x100),r7
        test_cc         1 1 1 0
        test_h_gr       0xdead,r7

        pass

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.