OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [addxcc.cgs] - Rev 840

Compare with Previous | Blame | View Log

# frv testcase for addxcc $GRi,$GRj,$GRk,$ICCi_1
# mach: all

        .include "testutils.inc"

        start

        .global addxcc
addxcc:
        set_gr_immed    1,gr7
        set_gr_immed    2,gr8
        set_icc         0x0e,0          ; Make sure carry bit is off
        addxcc          gr7,gr8,gr8,icc0
        test_icc        0 0 0 0 icc0
        test_gr_immed   3,gr8

        set_gr_limmed   0x7fff,0xffff,gr7
        set_gr_immed    1,gr8
        set_icc         0x04,0          ; Make sure carry bit is off
        addxcc          gr7,gr8,gr8,icc0
        test_icc        1 0 1 0 icc0
        test_gr_limmed  0x8000,0x0000,gr8

        set_icc         0x08,0          ; Make sure carry bit is off
        addxcc          gr8,gr8,gr8,icc0
        test_icc        0 1 1 1 icc0
        test_gr_immed   0,gr8

        set_gr_immed    1,gr7
        set_gr_immed    2,gr8
        set_icc         0x0f,0          ; Make sure carry bit is on
        addxcc          gr7,gr8,gr8,icc0
        test_icc        0 0 0 0 icc0
        test_gr_immed   4,gr8

        set_gr_limmed   0x7fff,0xffff,gr7
        set_gr_immed    0,gr8
        set_icc         0x05,0          ; Make sure carry bit is on
        addxcc          gr7,gr8,gr8,icc0
        test_icc        1 0 1 0 icc0
        test_gr_limmed  0x8000,0x0000,gr8

        set_gr_limmed   0x7fff,0xffff,gr7
        set_icc         0x0b,0          ; Make sure carry bit is on
        addxcc          gr7,gr8,gr8,icc0
        test_icc        0 1 0 1 icc0
        test_gr_immed   0,gr8

        pass

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.