OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [bcgelr.cgs] - Rev 827

Go to most recent revision | Compare with Previous | Blame | View Log

# frv testcase for bcgelr $ICCi,$ccond,$hint
# mach: all

        .include "testutils.inc"

        start

        .global bcgelr
bcgelr:
        ; ccond is true
        set_spr_immed   128,lcr
        set_spr_addr    ok1,lr
        set_icc         0x0 0
        bcgelr          icc0,0,0
        fail
ok1:
        set_spr_addr    ok2,lr
        set_icc         0x1 1
        bcgelr          icc1,0,1
        fail
ok2:
        set_spr_addr    bad,lr
        set_icc         0x2 2
        bcgelr          icc2,0,2

        set_spr_addr    bad,lr
        set_icc         0x3 3
        bcgelr          icc3,0,3

        set_spr_addr    ok5,lr
        set_icc         0x4 0
        bcgelr          icc0,0,0
        fail
ok5:
        set_spr_addr    ok6,lr
        set_icc         0x5 1
        bcgelr          icc1,0,1
        fail
ok6:
        set_spr_addr    bad,lr
        set_icc         0x6 2
        bcgelr          icc2,0,2

        set_spr_addr    bad,lr
        set_icc         0x7 3
        bcgelr          icc3,0,3

        set_spr_addr    bad,lr
        set_icc         0x8 0
        bcgelr          icc0,0,0

        set_spr_addr    bad,lr
        set_icc         0x9 1
        bcgelr          icc1,0,1

        set_spr_addr    okb,lr
        set_icc         0xa 2
        bcgelr          icc2,0,2
        fail
okb:
        set_spr_addr    okc,lr
        set_icc         0xb 3
        bcgelr          icc3,0,3
        fail
okc:
        set_spr_addr    bad,lr
        set_icc         0xc 0
        bcgelr          icc0,0,0

        set_spr_addr    bad,lr
        set_icc         0xd 1
        bcgelr          icc1,0,1

        set_spr_addr    okf,lr
        set_icc         0xe 2
        bcgelr          icc2,0,2
        fail
okf:
        set_spr_addr    okg,lr
        set_icc         0xf 3
        bcgelr          icc3,0,3
        fail
okg:

        ; ccond is true
        set_spr_immed   1,lcr
        set_spr_addr    okh,lr
        set_icc         0x0 0
        bcgelr          icc0,1,0
        fail
okh:
        set_spr_immed   1,lcr
        set_spr_addr    oki,lr
        set_icc         0x1 1
        bcgelr          icc1,1,1
        fail
oki:
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_icc         0x2 2
        bcgelr          icc2,1,2

        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_icc         0x3 3
        bcgelr          icc3,1,3

        set_spr_immed   1,lcr
        set_spr_addr    okl,lr
        set_icc         0x4 0
        bcgelr          icc0,1,0
        fail
okl:
        set_spr_immed   1,lcr
        set_spr_addr    okm,lr
        set_icc         0x5 1
        bcgelr          icc1,1,1
        fail
okm:
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_icc         0x6 2
        bcgelr          icc2,1,2

        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_icc         0x7 3
        bcgelr          icc3,1,3

        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_icc         0x8 0
        bcgelr          icc0,1,0

        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_icc         0x9 1
        bcgelr          icc1,1,1

        set_spr_immed   1,lcr
        set_spr_addr    okr,lr
        set_icc         0xa 2
        bcgelr          icc2,1,2
        fail
okr:
        set_spr_immed   1,lcr
        set_spr_addr    oks,lr
        set_icc         0xb 3
        bcgelr          icc3,1,3
        fail
oks:
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_icc         0xc 0
        bcgelr          icc0,1,0

        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_icc         0xd 1
        bcgelr          icc1,1,1

        set_spr_immed   1,lcr
        set_spr_addr    okv,lr
        set_icc         0xe 2
        bcgelr          icc2,1,2
        fail
okv:
        set_spr_immed   1,lcr
        set_spr_addr    okw,lr
        set_icc         0xf 3
        bcgelr          icc3,1,3
        fail
okw:
        ; ccond is false
        set_spr_immed   128,lcr
        set_spr_addr    bad,lr
        set_icc         0x0 0
        bcgelr          icc0,1,0

        set_icc         0x1 1
        bcgelr          icc1,1,1

        set_icc         0x2 2
        bcgelr          icc2,1,2

        set_icc         0x3 3
        bcgelr          icc3,1,3

        set_icc         0x4 0
        bcgelr          icc0,1,0

        set_icc         0x5 1
        bcgelr          icc1,1,1

        set_icc         0x6 2
        bcgelr          icc2,1,2

        set_icc         0x7 3
        bcgelr          icc3,1,3

        set_icc         0x8 0
        bcgelr          icc0,1,0

        set_icc         0x9 1
        bcgelr          icc1,1,1

        set_icc         0xa 2
        bcgelr          icc2,1,2

        set_icc         0xb 3
        bcgelr          icc3,1,3

        set_icc         0xc 0
        bcgelr          icc0,1,0

        set_icc         0xd 1
        bcgelr          icc1,1,1

        set_icc         0xe 2
        bcgelr          icc2,1,2

        set_icc         0xf 3
        bcgelr          icc3,1,3

        ; ccond is false
        set_spr_immed   1,lcr
        set_spr_addr    bad,lr
        set_icc         0x0 0
        bcgelr          icc0,0,0

        set_spr_immed   1,lcr
        set_icc         0x1 1
        bcgelr          icc1,0,1

        set_spr_immed   1,lcr
        set_icc         0x2 2
        bcgelr          icc2,0,2

        set_spr_immed   1,lcr
        set_icc         0x3 3
        bcgelr          icc3,0,3

        set_spr_immed   1,lcr
        set_icc         0x4 0
        bcgelr          icc0,0,0

        set_spr_immed   1,lcr
        set_icc         0x5 1
        bcgelr          icc1,0,1

        set_spr_immed   1,lcr
        set_icc         0x6 2
        bcgelr          icc2,0,2

        set_spr_immed   1,lcr
        set_icc         0x7 3
        bcgelr          icc3,0,3

        set_spr_immed   1,lcr
        set_icc         0x8 0
        bcgelr          icc0,0,0

        set_spr_immed   1,lcr
        set_icc         0x9 1
        bcgelr          icc1,0,1

        set_spr_immed   1,lcr
        set_icc         0xa 2
        bcgelr          icc2,0,2

        set_spr_immed   1,lcr
        set_icc         0xb 3
        bcgelr          icc3,0,3

        set_spr_immed   1,lcr
        set_icc         0xc 0
        bcgelr          icc0,0,0

        set_spr_immed   1,lcr
        set_icc         0xd 1
        bcgelr          icc1,0,1

        set_spr_immed   1,lcr
        set_icc         0xe 2
        bcgelr          icc2,0,2

        set_spr_immed   1,lcr
        set_icc         0xf 3
        bcgelr          icc3,0,3

        pass
bad:
        fail

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.