URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [cmsubhss.cgs] - Rev 840
Compare with Previous | Blame | View Log
# frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond# mach: frv fr500 fr400.include "testutils.inc"start.global cmsubhsscmsubhss:set_spr_immed 0x1b1b,cccrset_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0x0000,0x0000,fr11cmsubhss fr10,fr11,fr12,cc0,1test_fr_limmed 0x0000,0x0000,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0xdead,0x0000,fr10set_fr_iimmed 0x0000,0xbeef,fr11cmsubhss fr10,fr11,fr12,cc0,1test_fr_limmed 0xdead,0x4111,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0xbeef,0x0000,fr11cmsubhss fr10,fr11,fr12,cc0,1test_fr_limmed 0x4111,0xdead,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0x1111,0x1111,fr11cmsubhss fr10,fr11,fr12,cc0,1test_fr_limmed 0x0123,0x4567,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0xffff,0xffff,fr11cmsubhss fr10,fr11,fr12,cc0,1test_fr_limmed 0x1235,0x5679,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x7ffe,0x7ffe,fr10set_fr_iimmed 0xfffe,0xffff,fr11cmsubhss fr10,fr11,fr12,cc4,1test_fr_limmed 0x7fff,0x7fff,fr12test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x0001,0x0002,fr11cmsubhss fr10,fr11,fr12,cc4,1test_fr_limmed 0x8000,0x8000,fr12test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x0002,0x0001,fr11cmsubhss fr10,fr11,fr12,cc4,1test_fr_limmed 0x8000,0x8000,fr12test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0001,0x0001,fr10set_fr_iimmed 0x8000,0x8000,fr11cmsubhss.p fr10,fr10,fr12,cc4,1cmsubhss fr11,fr10,fr13,cc4,1test_fr_limmed 0x0000,0x0000,fr12test_fr_limmed 0x8000,0x8000,fr13test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is settest_spr_bits 2,1,1,msr1 ; msr1.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0x0000,0x0000,fr11cmsubhss fr10,fr11,fr12,cc1,0test_fr_limmed 0x0000,0x0000,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0xdead,0x0000,fr10set_fr_iimmed 0x0000,0xbeef,fr11cmsubhss fr10,fr11,fr12,cc1,0test_fr_limmed 0xdead,0x4111,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0xbeef,0x0000,fr11cmsubhss fr10,fr11,fr12,cc1,0test_fr_limmed 0x4111,0xdead,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0x1111,0x1111,fr11cmsubhss fr10,fr11,fr12,cc1,0test_fr_limmed 0x0123,0x4567,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0xffff,0xffff,fr11cmsubhss fr10,fr11,fr12,cc1,0test_fr_limmed 0x1235,0x5679,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x7ffe,0x7ffe,fr10set_fr_iimmed 0xfffe,0xffff,fr11cmsubhss fr10,fr11,fr12,cc5,0test_fr_limmed 0x7fff,0x7fff,fr12test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x0001,0x0002,fr11cmsubhss fr10,fr11,fr12,cc5,0test_fr_limmed 0x8000,0x8000,fr12test_spr_bits 0x3c,2,0x4,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x0002,0x0001,fr11cmsubhss fr10,fr11,fr12,cc5,0test_fr_limmed 0x8000,0x8000,fr12test_spr_bits 0x3c,2,0x8,msr0 ; msr0.sie is settest_spr_bits 2,1,1,msr0 ; msr0.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0001,0x0001,fr10set_fr_iimmed 0x8000,0x8000,fr11cmsubhss.p fr10,fr10,fr12,cc5,0cmsubhss fr11,fr10,fr13,cc5,0test_fr_limmed 0x0000,0x0000,fr12test_fr_limmed 0x8000,0x8000,fr13test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 0x3c,2,0xc,msr1 ; msr0.sie is settest_spr_bits 2,1,1,msr1 ; msr1.ovf settest_spr_bits 1,0,1,msr0 ; msr0.aovf settest_spr_bits 0x7000,12,1,msr0 ; msr0.mtt setset_fr_iimmed 0xdead,0xbeef,fr12set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0x0000,0x0000,fr11cmsubhss fr10,fr11,fr12,cc0,0test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0xdead,0x0000,fr10set_fr_iimmed 0x0000,0xbeef,fr11cmsubhss fr10,fr11,fr12,cc0,0test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0xbeef,0x0000,fr11cmsubhss fr10,fr11,fr12,cc0,0test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0x1111,0x1111,fr11cmsubhss fr10,fr11,fr12,cc0,0test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0xffff,0xffff,fr11cmsubhss fr10,fr11,fr12,cc0,0test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x7ffe,0x7ffe,fr10set_fr_iimmed 0xfffe,0xffff,fr11cmsubhss fr10,fr11,fr12,cc4,0test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x0001,0x0002,fr11cmsubhss fr10,fr11,fr12,cc4,0test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x0002,0x0001,fr11cmsubhss fr10,fr11,fr12,cc4,0test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0xbeef,0xdead,fr13set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0001,0x0001,fr10set_fr_iimmed 0x8000,0x8000,fr11cmsubhss.p fr10,fr10,fr12,cc4,0cmsubhss fr11,fr10,fr13,cc4,0test_fr_limmed 0xdead,0xbeef,fr12test_fr_limmed 0xbeef,0xdead,fr13test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0xdead,0xbeef,fr12set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0x0000,0x0000,fr11cmsubhss fr10,fr11,fr12,cc1,1test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0xdead,0x0000,fr10set_fr_iimmed 0x0000,0xbeef,fr11cmsubhss fr10,fr11,fr12,cc1,1test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0xbeef,0x0000,fr11cmsubhss fr10,fr11,fr12,cc1,1test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0x1111,0x1111,fr11cmsubhss fr10,fr11,fr12,cc1,1test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0xffff,0xffff,fr11cmsubhss fr10,fr11,fr12,cc1,1test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x7ffe,0x7ffe,fr10set_fr_iimmed 0xfffe,0xffff,fr11cmsubhss fr10,fr11,fr12,cc5,1test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x0001,0x0002,fr11cmsubhss fr10,fr11,fr12,cc5,1test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x0002,0x0001,fr11cmsubhss fr10,fr11,fr12,cc5,1test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0xbeef,0xdead,fr13set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0001,0x0001,fr10set_fr_iimmed 0x8000,0x8000,fr11cmsubhss.p fr10,fr10,fr12,cc5,1cmsubhss fr11,fr10,fr13,cc5,1test_fr_limmed 0xdead,0xbeef,fr12test_fr_limmed 0xbeef,0xdead,fr13test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0xdead,0xbeef,fr12set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0x0000,0x0000,fr11cmsubhss fr10,fr11,fr12,cc2,1test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0xdead,0x0000,fr10set_fr_iimmed 0x0000,0xbeef,fr11cmsubhss fr10,fr11,fr12,cc2,0test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0xbeef,0x0000,fr11cmsubhss fr10,fr11,fr12,cc2,1test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0x1111,0x1111,fr11cmsubhss fr10,fr11,fr12,cc2,0test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0xffff,0xffff,fr11cmsubhss fr10,fr11,fr12,cc2,1test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x7ffe,0x7ffe,fr10set_fr_iimmed 0xfffe,0xffff,fr11cmsubhss fr10,fr11,fr12,cc6,0test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x0001,0x0002,fr11cmsubhss fr10,fr11,fr12,cc6,1test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x0002,0x0001,fr11cmsubhss fr10,fr11,fr12,cc6,0test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0xbeef,0xdead,fr13set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0001,0x0001,fr10set_fr_iimmed 0x8000,0x8000,fr11cmsubhss.p fr10,fr10,fr12,cc6,1cmsubhss fr11,fr10,fr13,cc6,0test_fr_limmed 0xdead,0xbeef,fr12test_fr_limmed 0xbeef,0xdead,fr13test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set;set_fr_iimmed 0xdead,0xbeef,fr12set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0000,0x0000,fr10set_fr_iimmed 0x0000,0x0000,fr11cmsubhss fr10,fr11,fr12,cc3,1test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0xdead,0x0000,fr10set_fr_iimmed 0x0000,0xbeef,fr11cmsubhss fr10,fr11,fr12,cc3,0test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x0000,0xdead,fr10set_fr_iimmed 0xbeef,0x0000,fr11cmsubhss fr10,fr11,fr12,cc3,1test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0x1111,0x1111,fr11cmsubhss fr10,fr11,fr12,cc3,0test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0x1234,0x5678,fr10set_fr_iimmed 0xffff,0xffff,fr11cmsubhss fr10,fr11,fr12,cc3,1test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x7ffe,0x7ffe,fr10set_fr_iimmed 0xfffe,0xffff,fr11cmsubhss fr10,fr11,fr12,cc7,0test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x0001,0x0002,fr11cmsubhss fr10,fr11,fr12,cc7,1test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_spr_immed 0,msr0set_fr_iimmed 0x8001,0x8001,fr10set_fr_iimmed 0x0002,0x0001,fr11cmsubhss fr10,fr11,fr12,cc7,0test_fr_limmed 0xdead,0xbeef,fr12test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setset_fr_iimmed 0xbeef,0xdead,fr13set_spr_immed 0,msr0set_spr_immed 0,msr1set_fr_iimmed 0x0001,0x0001,fr10set_fr_iimmed 0x8000,0x8000,fr11cmsubhss.p fr10,fr10,fr12,cc7,1cmsubhss fr11,fr10,fr13,cc7,0test_fr_limmed 0xdead,0xbeef,fr12test_fr_limmed 0xbeef,0xdead,fr13test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is cleartest_spr_bits 2,1,0,msr0 ; msr0.ovf not settest_spr_bits 1,0,0,msr0 ; msr0.aovf not settest_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not setpass