OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-old/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [cstf.cgs] - Rev 840

Compare with Previous | Blame | View Log

# frv testcase for cstf $FRk,@($GRi,$GRj),$CCi,$cond
# mach: all

        .include "testutils.inc"

        start

        .global cstf
cstf:
        set_spr_immed   0x1b1b,cccr
        set_gr_gr       sp,gr20

        set_mem_limmed  0xdead,0xbeef,sp
        set_gr_immed    0,gr7
        set_fr_iimmed   0xffff,0xffff,fr8
        cstf            fr8,@(sp,gr7),cc0,1
        test_mem_limmed 0xffff,0xffff,gr20

        set_gr_immed    4,gr7
        inc_gr_immed    -4,sp
        set_fr_iimmed   0xeeee,0xeeee,fr8
        cstf            fr8,@(sp,gr7),cc0,1
        test_mem_limmed 0xeeee,0xeeee,gr20

        set_gr_immed    -4,gr7
        inc_gr_immed    8,sp
        set_fr_iimmed   0xdddd,0xdddd,fr8
        cstf            fr8,@(sp,gr7),cc4,1
        test_mem_limmed 0xdddd,0xdddd,gr20

        set_gr_gr       gr20,sp
        set_mem_limmed  0xdead,0xbeef,sp
        set_gr_immed    0,gr7
        set_fr_iimmed   0xffff,0xffff,fr8
        cstf            fr8,@(sp,gr7),cc0,0
        test_mem_limmed 0xdead,0xbeef,gr20

        set_gr_immed    4,gr7
        inc_gr_immed    -4,sp
        set_fr_iimmed   0xeeee,0xeeee,fr8
        cstf            fr8,@(sp,gr7),cc0,0
        test_mem_limmed 0xdead,0xbeef,gr20

        set_gr_immed    -4,gr7
        inc_gr_immed    8,sp
        set_fr_iimmed   0xdddd,0xdddd,fr8
        cstf            fr8,@(sp,gr7),cc4,0
        test_mem_limmed 0xdead,0xbeef,gr20

        set_gr_gr       gr20,sp
        set_mem_limmed  0xdead,0xbeef,sp
        set_gr_immed    0,gr7
        set_fr_iimmed   0xffff,0xffff,fr8
        cstf            fr8,@(sp,gr7),cc1,0
        test_mem_limmed 0xffff,0xffff,gr20

        set_gr_immed    4,gr7
        inc_gr_immed    -4,sp
        set_fr_iimmed   0xeeee,0xeeee,fr8
        cstf            fr8,@(sp,gr7),cc1,0
        test_mem_limmed 0xeeee,0xeeee,gr20

        set_gr_immed    -4,gr7
        inc_gr_immed    8,sp
        set_fr_iimmed   0xdddd,0xdddd,fr8
        cstf            fr8,@(sp,gr7),cc5,0
        test_mem_limmed 0xdddd,0xdddd,gr20

        set_gr_gr       gr20,sp
        set_mem_limmed  0xdead,0xbeef,sp
        set_gr_immed    0,gr7
        set_fr_iimmed   0xffff,0xffff,fr8
        cstf            fr8,@(sp,gr7),cc1,1
        test_mem_limmed 0xdead,0xbeef,gr20

        set_gr_immed    4,gr7
        inc_gr_immed    -4,sp
        set_fr_iimmed   0xeeee,0xeeee,fr8
        cstf            fr8,@(sp,gr7),cc1,1
        test_mem_limmed 0xdead,0xbeef,gr20

        set_gr_immed    -4,gr7
        inc_gr_immed    8,sp
        set_fr_iimmed   0xdddd,0xdddd,fr8
        cstf            fr8,@(sp,gr7),cc5,1
        test_mem_limmed 0xdead,0xbeef,gr20

        set_gr_gr       gr20,sp
        set_mem_limmed  0xdead,0xbeef,sp
        set_gr_immed    0,gr7
        set_fr_iimmed   0xffff,0xffff,fr8
        cstf            fr8,@(sp,gr7),cc2,0
        test_mem_limmed 0xdead,0xbeef,gr20

        set_gr_immed    4,gr7
        inc_gr_immed    -4,sp
        set_fr_iimmed   0xeeee,0xeeee,fr8
        cstf            fr8,@(sp,gr7),cc2,1
        test_mem_limmed 0xdead,0xbeef,gr20

        set_gr_immed    -4,gr7
        inc_gr_immed    8,sp
        set_fr_iimmed   0xdddd,0xdddd,fr8
        cstf            fr8,@(sp,gr7),cc6,0
        test_mem_limmed 0xdead,0xbeef,gr20

        set_gr_gr       gr20,sp
        set_mem_limmed  0xdead,0xbeef,sp
        set_gr_immed    0,gr7
        set_fr_iimmed   0xffff,0xffff,fr8
        cstf            fr8,@(sp,gr7),cc3,1
        test_mem_limmed 0xdead,0xbeef,gr20

        set_gr_immed    4,gr7
        inc_gr_immed    -4,sp
        set_fr_iimmed   0xeeee,0xeeee,fr8
        cstf            fr8,@(sp,gr7),cc3,0
        test_mem_limmed 0xdead,0xbeef,gr20

        set_gr_immed    -4,gr7
        inc_gr_immed    8,sp
        set_fr_iimmed   0xdddd,0xdddd,fr8
        cstf            fr8,@(sp,gr7),cc7,1
        test_mem_limmed 0xdead,0xbeef,gr20

        pass

Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.